LTC3811_15 Datasheet, PDF (32/48 Pages) Linear Technology – High Speed Dual, Multiphase Step-Down DC/DC Controller

LTC3811
APPLICATIONS INFORMATION
node voltage, SW, rises to V_IN and the BOOST pin follows.
With the topside MOSFET on, the boost voltage is above
the input supply: V_BOOST = V_IN + V_DRVCC. The value of the
boost capacitor C_B needs to be 100 times that of the total
input capacitance of the topside MOSFET(s). The reverse
breakdown of the external Schottky diode must be greater
than V_IN(MAX). When adjusting the gate drive level, the
final arbiter is the total input current for the regulator. If
V_X (MASTER)
V_OUT (SLAVE)
TIME
3811 F19a
(19a) Coincident Tracking
V_X (MASTER)
a change is made and the input current decreases, then
the efficiency has improved. If there is no change in input
current, then there is no change in efficiency.
Overvoltage Protection
The LTC3811 contains a comparator that monitors the
FB pin voltage for potential overvoltage conditions. This
comparator (OV in the Functional Diagram) detects when
the FB pin voltage exceeds 0.66V, or is 10% above nominal
regulation. When this condition is sensed, the top MOSFET
is turned off and the bottom MOSFET is turned on. For an
overvoltage condition that persists, the inductor current will
reverse until the negative current limit of the converter is
reached. If the OV condition terminates V_OUT will return to
regulation and normal operation automatically resumes.
The OV signal that controls the top and bottom MOSFET
switching does not propagate through the PGOOD filter
before action is taken. The OV comparator is capable of
sensing a fault condition within 100ns to 200ns, after
which the top MOSFET is turned off. The PGOOD filter
will delay the signal to the open-drain NMOS transistor
connected to the PGOOD pin, however, preventing OV (and
UV) transients of less than about 130μs from forcing a
system reset.
V_OUT (SLAVE)
TIME
3811 F19b
(19b) Ratiometric Tracking
Figure 19. Two different Modes of Output Votlage Tracking
V_x V_OUT
R_TRACKB
R_TRACKA
R_B
LTC3811
V_FB
R_A
2.5μA
SS/TRACK
3811 F20
Figure 20. Using the SS/TRACK Pin for Tracking
Phase-Locked Loop and Frequency Synchronization
The LTC3811 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the MODE/SYNC pin. The turn-on
phase of controller 2’s top MOSFET is controlled by the
voltage on the PHASEMODE pin. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of comple-
mentary current sources that charge or discharge the
external filter network connected to the PLL/LPF pin. The
relationship between the voltage on the PLL/LPF pin and
operating frequency, when there is a clock signal applied
3811f
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