LTC3811_15 Datasheet, PDF (35/48 Pages) Linear Technology – High Speed Dual, Multiphase Step-Down DC/DC Controller

LTC3811
APPLICATIONS INFORMATION
will provide adequate phase margin at the unity-gain
frequency of the loop.
In a Type-II compensation scheme, the zero is typically
placed below the target unity-gain frequency, depending
upon the desired settling time of the converter, and the pole
is placed no higher than half the switching frequency in
order to attenuate the switching frequency from the loop.
The gain between the zero and pole is typically adjusted
until the desired phase margin is achieved.
In general, the output capacitor is chosen based on cost
and size considerations, given a certain error budget
due to output ripple voltage and load transient response.
Oftentimes, multiple capacitor types (such as ceramic
and special polymer) are connected in parallel in order
to achieve a good combination of bulk capacitance and
low ESR. In general, the output capacitor is not normally
chosen to optimize the bode response.
Due to their small case size and low ESR, ceramic output
capacitors are well suited to very low voltage, high current
applications. Their low ESR and relatively high RMS current
capability make them a good choice for today’s demand-
ing processor-based loads. A fully ceramic output stage,
however, will result in very low ESR, pushing the ESR zero
frequency relatively close to the unity-gain frequency of the
loop. In this case a Type-III compensation network using
3 poles and 2 zeros may be necessary (see Figure 24). For
particularly demanding applications requirements, please
consult Linear Technology’s Applications department.
V_OUT
R2
R1
0.6V
C1
C2
R3
–
EA
+
V_OUT
R2
R1
R4
C3
0.6V
C1
C2
R3
–
EA
+
f _P1
=
2π
•
1
R2 (C1 +
C2)
fP2 =
2π
1
•
R3
⎛
⎝⎜
C1 •
C1 +
C2 ⎞
C2⎠⎟
fZ
=
1
2π • R3 • C2
30
f_Z
20
–20dB
10 _DECADE
f_P2
A_V
=
20
log
•
R3
R1
–20dB/DECADE
f
f
–45
–90
3811 F23
Figure 23. Type-II Compensation Network and
Frequency Response
fP1
=
2π
•
1
R2 (C1 +
C2)
fP2
=
1
2π
•
R3
⎛
⎝⎜
C1 •
C1 +
C2 ⎞
C2⎠⎟
fP3
=
1
2 π • R4 • C3
fZ1 =
1
2 π • R3 • C2
fZ2
=
2π•
(R2
1
+
R4)
•
C3
30
f_Z1
f_Z2 f_P2
f_P3
20
10 _–20dB
DECADE
–20dB/DECADE
f
90
45
0
f
–45
–90
3811 F24
Figure 24. Type-III Compensation Network and
Frequency Response
3811f
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