LTC3811_15 Datasheet, PDF (21/48 Pages) Linear Technology – High Speed Dual, Multiphase Step-Down DC/DC Controller

LTC3811
OPERATION (Refer to the Functional Diagram)
x-axis. The output ripple current is normalized against
the inductor ripple current at zero duty factor. The graph
can be used in place of tedious calculations. As shown in
Figure 6, the zero output ripple current is obtained
when:
V_OUT
V_IN
=
k
N
where k = 1, 2, ..., N – 1
So the number of phases used can be selected to minimize
the output ripple current and therefore the output ripple
voltage at the given input and output voltages. In appli-
cations having a highly varying input voltage, additional
phases will produce the best results.
Accepting larger values of ΔI_L allows the use of low in-
ductances, but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is
ΔI_L = 0.4(I_OUT)/N, where N is the number of channels and
I_OUT is the total load current. Remember, the maximum
ΔI_L occurs at the maximum input voltage. The individual
inductor ripple currents are constant determined by the
inductor, input and output voltages.
1.0
0.9
1-PHASE
2-PHASE
0.8
3-PHASE
4-PHASE
0.7
6-PHASE
0.6
0.5
0.4
0.3
0.2
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY FACTOR (V_OUT/V_IN)
3811 F06
Figure 6. Normalized Peak Output Current vs
Duty factor [I_RMS ≈ 0.3(ΔI_O(P-P))]
Power Good Pins (PGOOD1, PGOOD2)
Each PGOOD pin is connected to the open drain of an
internal N-channel pull-down MOSFET. The MOSEFT turns
on and pulls the PGOOD pin low when the corresponding
FB pin is outside a ±10% window around the 0.6V refer-
ence voltage. The PGOOD pin is also pulled low when the
corresponding RUN pin is low, or during an undervoltage
lockout or overtemperature condition. When the FB pin
voltage is within the ±10% window, the internal PGOOD
MOSFET is turned off and the pin is normally pulled up by
an external resistor. The absolute maximum voltage rating
of the PGOOD pins is 7V.
The PGOOD logic contains separate filters depending on
whether the controller is entering or exiting a fault condi-
tion. When the FB pin is exiting a fault condition (such as
during normal output voltage start-up, prior to regulation),
the PGOOD pin will remain low for an additional 30μs. This
allows the output voltage to reach steady-state regulation
and prevents the enabling of a heavy load from re-triggering
a UVLO condition. When the FB pin is entering either an
undervoltage, UV, or overvoltage, OV, fault condition, the
PGOOD pin will remain high 130μs after the onset of the
fault. This non-integrating filter prevents noise or short
duration overload conditions from triggering the PGOOD
outputs and causing a false system reset. Figure 7 illustrates
the timing diagram for a hypothetical undervoltage event
on the FB pin, and the resulting PGOOD waveform.
In multiphase applications, one error amplifier is used to
control all of the phase current comparators. In addition,
since the FB pins for the unused error amplifiers are con-
nected to INTV_CC (in order to three-state these amplifiers),
the PGOOD outputs for these amplifiers will be asserted.
In order to prevent falsely reporting a fault condition, the
0.66V = OV
0.7
THRESHOLD
0.6
0.5
0.54V = UV
THRESHOLD
0.4
0.3
0.2
0.1
0
TIME
5
t < 30μs
130μs
30μs
0
TIME 3811 F07
Figure 7. PGOOD Filter Timing Diagram
3811f
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