LTC3589_1 Datasheet, PDF (35/46 Pages) Linear Technology – 8-Output Regulator with Sequencing and I2C

LTC3589
OPERATION
I²C Slave Address
The LTC3589 responds to factory programmed read and
write addresses. The write address is 0x68. The read ad-
dress is 0x69. The least significant bit of the address byte,
known as the read/write bit, is 0 when writing data to the
LTC3589 and 1 when reading from it.
I²C Sub-Addressed Writing
The LTC3589 has 14 command registers for control inputs.
They are accessed by the I²C port via a sub-addressed
writing system.
Each write cycle of the LTC3589 consists of a series of three
or more bytes beginning with the LTC3589 write address.
The second byte is the sub address of the command reg-
ister being written to. The sub address is a pointer to the
register where the data in the third byte will be stored. The
third byte is the data to be written to the just-received sub
address. Continue alternating sub address and data bytes
to write multiple registers in a single START sequence.
I²C Bus Write Operation
The master initiates communication with the LTC3589
with a START condition and the LTC3589’s write address.
If the address matches that of the LTC3589, the LTC3589
returns an acknowledge pulse. The master should then
deliver the sub address. Again the LTC3589 acknowledges
and the cycle is repeated for the data byte. The data byte
is transferred to an internal holding latch upon the return
of its acknowledge by the LTC3589. Continue writing sub
address and data pairs into the holding latches. Address-
ing the LTC3589 is not required for each sub address and
data pair. If desired a REPEAT-START condition may be
initiated by the master where another device on the I²C
bus is addressed. The LTC3589 remembers the valid data
it has received. Once all the devices on the I²C have been
addressed and sent valid data and a global STOP has been
sent, the LTC3589 will update its command latches with
the data it has received.
I²C Sub-Addressed Reading
The LTC3589 I²C interface supports random address
reading of the I²C command and status registers. Before
reading a register, the registers sub address must be
written. Send a START condition followed by the LTC3589
write address followed by the sub address of the register
to be read. The sub address is now stored as a pointer
to the register. Send a REPEAT-START condition followed
by the LTC3589 read address. Following the acknowledg-
ment of its read address the LTC3589 returns one bit of
information for each of the next 8 clock cycles. A STOP
condition is not required for the read operation. The read
sub address is stored until a new sub address is written.
Verify the data written to the internal data hold latches
prior to committing date to the command registers by
reading back the data before sending a STOP condition.
Continuously poll a register by repeatedly sending a START
condition followed by the LTC3589 read address, and then
clocking the data out after the read address acknowledge.
ADDRESS
0 1 1 0 1 0 0 WR
SUB ADDRESS
S7 S6 S5 S4 S3 S2 S1 S0
ADDRESS
0 1 1 0 1 0 0 RD
DATA
R7 R6 R5 R4 R3 R2 R1 R0
START
SDA
0 1 1 0 1 0 0 0 ACK
START
ACK
0 1 1 0 1 0 0 1 ACK
STOP
ACK
SCL
123456789123456789
123456789123456789
3589 F20
Figure 20. LTC3589 I²C Serial Port Read Pattern
3589fb
35