LTC3589_1 Datasheet, PDF (34/46 Pages) Linear Technology – 8-Output Regulator with Sequencing and I2C

LTC3589
OPERATION
I²C Bus Speed
The I²C port operates at speeds up to 400kHz. It has
built-in timing delays to ensure correct operation when
addressed from an I²C compliant master device. It also
contains input filters designed to suppress glitches should
the bus become corrupted.
I²C START and STOP Conditions
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to the
LTC3589, the master may transmit a STOP condition that
commands the LTC3589 to act upon its new command
set. A STOP condition is sent by the master by transition-
ing SDA from LOW to HIGH while SCL is HIGH. The bus
it then free for communication with another I²C device.
I²C Byte Format
Each byte sent to or received from the LTC3589 must
be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3589
most significant bit (MSB) first.
I²C Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3589 is written to,
it acknowledges its write address and subsequent register
address and data bytes. When reading from the LTC3589,
it acknowledges its read address and 8-bit status byte.
An acknowledge pulse (active LOW) generated by the
LTC3589 lets the master know that the latest byte of
information was transferred. The master generates the
clock cycle and releases the SDA line (HIGH) during the
acknowledge clock cycle. The LTC3589 pulls down the SDA
line during the write acknowledge clock pulse so that it is
a stable LOW during the HIGH period of this clock pulse.
SDA
t_LOW
t_{SU, DAT}
SCL
t_{HD, STA}
START
CONDITION
t_HIGH
t_r
t_f
t_{HD, DAT}
t_{HD, STA}
t_{HD, STA}
t_SP
REPEATED START
CONDITION
Figure 18. LTC3589 I²C Timing
t_BUF
t_{SU, STO}
3589 F18
STOP
START
ADDRESS
0 1 1 0 1 0 0 WR
SUB ADDRESS
S7 S6 S5 S4 S3 S2 S1 S0
DATA
D7 D6 D5 D4 D3 D2 D1 D0
SUB ADDRESS
S7 S6 S5 S4 S3 S2 S1 S0
DATA
D7 D6 D5 D4 D3 D2 D1 D0
START
STOP
SDA
0 1 1 0 1 0 0 0 ACK
ACK
ACK
ACK
ACK
SCL
1 234567 89 1 234567 89 1 234567 89 1 234567 89 1 234567 89
3589 F19
Figure 19. LTC3589 I²C Serial Port Multiple Write Pattern
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