LTC3589_1 Datasheet, PDF (30/46 Pages) Linear Technology – 8-Output Regulator with Sequencing and I2C

LTC3589
OPERATION
allow the regulator outputs to discharge. If the PWR_ON
pin is LOW at the end of the power-down time, the LTC3589
will remain in sleep mode with just the always-active LDO
operating. If PWR_ON is HIGH at the end of one second and
the fault condition has cleared, the LTC3589 will power-up
in the same way shown in Figure 8. Neither IRQ nor the
status registers are cleared by the fault induced shutdown.
FAULT
ON(PB)
PBSTAT
WAKE
PWR_ON
<1 SEC
µC/µP CONTROL
IRQ
CLIRQ
3589 F10
Figure 10. Hard Reset Due to a Fault Condition
ENABLE AND POWER-ON SEQUENCING
Enable Input Pin Operation
The regulator enable input pins facilitate pin-strapping an
output rail to the enable pin of the next regulator in the
desired sequence. The regulator enable inputs normally
have a 0.8V (typical) input threshold. If any enable is driven
HIGH, the remaining enable input thresholds switch to a
more accurate 500mV (typical) threshold.
Figure 11 shows an application circuit for a typical pin-
strapped start-up sequence. Holding ON LOW for 400ms
PWR_ON
LTC3589
EN1
WAKE
EN2
SW1
EN3
SW2
EN4
SW3
EN_LDO2 BB_OUT
EN_LDO34
LDO2
ON
LDO3
PWR_ON
LDO4
3589 F11
1V TO 1.2V
1.8V
0.8V TO 1V
3.3V
1.2V
1.8V
2.8V
Figure 11. Pin-Strap Start-Up Sequence Application Circuit
30
brings up the WAKE pin that is tied to EN1 and EN3 to
enable step-down switching regulators 1 and 3. The output
of regulator 1 is tied to EN2 and EN4 that enables step-
down switching regulator 2 and the buck-boost switching
regulator 4. The output of step-down switching regulator 2
is tied to EN_LDO2 and EN_LDO3 to enable LDO2, LDO3
and LDO4. Within five seconds of WAKE going HIGH, the
microprocessor or microcontroller must drive PWR_ON
HIGH to tell LTC3589 that rails are good and to stay in the
power-on state.
Figure 12 shows the start-up timing for the application
shown in Figure 11. There is a 200µs (typical) delay
between the enable pin and the internal enable signal to
each regulator.
WAKE
0.5V ^200µs
1.2V
V1
1V
V3
V2 ^0.5V
200µs
1.8V
3.3V
V4
LDO2
1.2V
200µs
1.8V
LDO3
2.8V
LDO4
3589 F12
Figure 12. Pin-Strap Sequencing Timing
Depending on settings in I²C system control register 2
(SCR2), a regulator’s output must discharge to less than
300mV before it will respond to its enable. The output
discharge feature is to guarantee proper start-up sequenc-
ing. This feature and the 2.5k pull-down resistors may be
overridden by bit settings in command register SCR2.
Keep-Alive Operation
For systems which require an active supply rail when in
system standby, any of the three LTC3589 step-down
switching regulators or LDO2 may be kept alive regard-
less of the status of PWR_ON and WAKE. Writing a 1 to
a regulator’s keep-alive bit in its dynamic target voltage
register will keep a regulator alive when the LTC3589 is
in standby mode. A regulator with its keep-alive bit set
will stay enabled until the bit is reset writing the bit LOW,
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