LTC3589_1 Datasheet, PDF (18/46 Pages) Linear Technology – 8-Output Regulator with Sequencing and I2C

LTC3589
OPERATION
To help reduce LDO power loss in the system, the regula-
tors have dedicated supply inputs that may be lower than
the main V_IN supply. Connect a low ESR 1µF capacitor to
each of the output pins LDO2, LDO3, and LDO4.
LDO Regulator 2
One of the LTC3589 dynamic slewing DACs serves as the
reference input of LDO2. The output range of LDO2 is set
using an external resistor divider connected from LDO2
to the feedback pin LDO2_FB, as shown in Figure 2. Set
the output voltage of LDO2 using the following formula:
V_OUT

= _1+

R1^
R2_
•
(0.3625 + L2DTVx
•
0.0125)
L2DTVx is the five bit word contained in the LDO2 dynamic
target voltage 1 (L2DTV1) or the LDO2 dynamic target
voltage 2 (L2DTV2) command registers. The default value
of L2DTVx[4-0] is 11001 to output a reference voltage
of 0.675V. LDO2 is enabled by writing bit 4 in the output
voltage enable (OVEN) command register to 1 or driving
the LDO2_EN pin high. Whenever the command is given to
slew LDO2 DAC reference to a lower voltage an integrated
2.5k pull-down resistor is connected to LDO2 output.
0.3625V
TO 0.75V
PV_IN
EA
LDO2
R1
1µF
FB
R2
DAC
5
3589 F02
Figure 2. LDO2 Application Circuit
Table 1. Shows the I²C command register settings used
to control LDO2.
Table 1. LDO 2 Command Register Settings
COMMAND
VALUE SETTING
REGISTER[BIT]
OVEN[4]
SCR2[4]
VCCR[5]
0* Disable
1 Enable
0* Wait for Output Below 300mV Before Enable
1 Enable Immediately
0* Select Register L2DTV1 (V1) Reference
1 Select Register L2DTV2 (V2) Reference
VCCR[6]
VRRCR[7-6]
1 Initiate Dynamic Voltage Slew
00 Reference Slew Rate = 0.88mV/µs
01 Reference Slew Rate = 1.75mV/µs
10 Reference Slew Rate = 3.5mV/µs
11* Reference Slew Rate = 7mV/µs
L2DTV1[4-0]
L2DTV1[5]
L2DTV1[7]
L2DTV2[4-0]
11001*
0*
1
0*
1
11001*
DAC Dynamic Target Voltage V1
Force PGOOD Low When Slewing
Normal PGOOD Operation When Slewing
Shutdown LDO2 Normally
Keep LDO2 Alive
DAC Dynamic Target Voltage V2
* Denotes Default Power-On Value
LDO Regulator 3
LDO3 is a fixed 1.8V output regulator. LDO3 is enabled
by driving pin EN_LDO34 high or by writing command
register OVEN[5] to 1.
Table 2 shows the I²C command register settings used
to control LDO3.
Table 2. LDO 3 Command Register Settings
COMMAND
VALUE SETTING
REGISTER[BIT]
OVEN[5]
0* Disable
1 Enable
SCR2[5]
0* Wait for Output Below 300mV Before Enable
1 Enable Immediately
* Denotes Default Power-On Value
3589fb
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