LTC3589_1 Datasheet, PDF (31/46 Pages) Linear Technology – 8-Output Regulator with Sequencing and I2C

LTC3589
OPERATION
resetting the LTC3589 with a pushbutton hard reset, or
a fault condition (UVLO, PGOOD, timeout or thermal
shutdown) occurs. PGOOD and fault status are reported
in the IRQSTAT and PGSTAT registers and on the IRQ and
PGOOD pins for keep-alive regulators when PWR_ON and
WAKE are LOW.
Software Control Mode
Once a power-up sequence is completed each regulator
may be enabled and disabled individually by the system
as needed for power mode requirements. Setting the out-
put voltage enable command register bit OVEN[7] HIGH
disconnects each regulator from its enable pin so control
is solely through the OVEN command register. To enter
software control mode, set command bit OVEN[7] HIGH
and the desired enable bits in OVEN[6:0] HIGH. Any of the
regulators enabled in OVEN[6:0] will stay on regardless
of the state of their enable pins when OVEN[7] is HIGH.
Setting the regulator enable bits and the software control
bit in OVEN[7] may occur on the same I²C start-stop
sequence. A normal shutdown using PWR_ON resets
all eight bits of the OVEN register to 0x00 to ensure all
regulators are shut off.
FAULT DETECTION, SHUTDOWN, AND REPORTING
The LTC3589 monitors V_IN, output rail voltages and internal
die temperature. A warning condition is indicated when
V_IN is less than 2.9V and when internal die temperature
approaches the thermal shutdown temperature. A fault
condition occurs when V_IN is less than 2.6V, any regulator
output is 8% low for 14ms, or the internal die temperature
is HIGH. Warning and fault states are reported via the IRQ,
PGOOD, and RTSO pins. Specific fault states are read via
the I²C serial port status registers IRQSTAT and PGSTAT.
RSTO Pin Function
The RSTO (reset output) pin is an open-drain output for
use as a power-on reset signal. It is pulled LOW at initial
power until LDO1 is within 8% of its target and the initial
one second start-up timer is finished. RSTO remains HIGH
during normal operation and will be pulled low if LDO1
loses regulation for more than 25µs or a pushbutton hard
reset is initiated. RSTO is released high 14ms after LDO1
returns to regulation.
Figure 13 shows a initial power-up for the RSTO pin. If
V_IN is not above its undervoltage thresholds at the end
of the 1 second start-up time, the IRQ pin will be pulled
LOW and an undervoltage bit will be set in the IRQSTAT
status register.
V_IN ^2.7V
LDO1
RSTO
1 SEC
INITIAL POWER-UP
>25µs
14ms
LDO1 UNDERVOLTAGE
3589 F13
Figure 13. Initial Power-Up and LDO1 Undervoltage RSTO Timing
PGOOD Pin and PGSTAT Status Register Function
Each LTC3589 regulator has an internal power good out-
put that is active whenever the regulators feedback pin is
closer than 7% (typical) from its input reference voltage.
If any of the internal power good signals indicate a low
voltage for longer than 25µs (typical), the PGOOD pin is
pulled LOW and the appropriate bit in the PGSTAT status
register (Table 14) is set.
Table 14. PGSTAT Read-Only Register Bit Definitions
PGSTAT[BIT] VALUE SETTING
0
0 LDO1_STBY Output Low
1 ^{LDO1_STBY Output Good}
1
0 Step-Down Switching Regulator 1 Output Low
1 ^{Step-Down Switching Regulator 1 Output Good}
2
0 Step-Down Switching Regulator 2 Output Low
1 ^{Step-Down Switching Regulator 2 Output Good}
3
0 Step-Down Switching Regulator 3 Output Low
1 ^{Step-Down Switching Regulator 3 Output Good}
4
0 Buck-Boost Regulator 4 Output Low
1 ^{Buck-Boost Regulator 4 Output Good}
5
0 LDO2 Output Low
1 ^{LDO2 Output Good}
6
0 LDO3 Output Low
1 ^{LDO3 Output Good}
7
0 LDO4 Output Low
1 ^{LDO4 Output Good}
3589fb
31