LTC3589_1 Datasheet, PDF (32/46 Pages) Linear Technology – 8-Output Regulator with Sequencing and I2C

LTC3589
OPERATION
Figure 14 shows the PGOOD pin and PGSTAT status reg-
ister timing. When no regulator is enabled, the PGOOD
pin is pulled LOW and PGSTAT bits are LOW. PGOOD and
the PGSTAT bits are HIGH 250µs after the last enabled
regulator is within 7% of its target.
WAKE
WAKE HIGH AFTER 1sec
IF PWR_ON HIGH
1sec
ENx
200µs
V_OUTx
PGOOD
250µs
IRQ
ENABLE
25µs
25µs
250µs
DISABLED IF
WAKE LOW
250µs
14ms
UNDERVOLTAGE
EXTENDED
UNDERVOLTAGE
(FAULT)
DISABLE
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V_IN drops below 2.55V, the fault condition initiates a hard
shutdown reset. Figure 15 shows undervoltage warning
and fault detection levels.
V_IN
UNDERVOLTAGE
FAULT
WARNING
2.55V 2.65V 2.9V
3V
V_IN
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Figure 15. UV Detection Hard Reset and Warning Levels
An undervoltage warning sets register bit IRQSTAT[4] and
pulls the IRQ pin LOW.
To minimize standby quiescent current the UVLO and
thermal sensor circuits are disabled when all the regula-
tors are off.
Figure 14. PGOOD Pin and PGSTAT Status Register Timing
If any enabled regulator output falls more than 7% low
for longer than 25µs PGOOD is pulled LOW and a cor-
responding status bit in the PGSTAT register is set to 0.
The PGOOD pin and PGSTAT status bit remain LOW for
as long as the low voltage condition persists plus 250µs.
An extended low output rail causing the PGOOD pin to
be LOW for longer than 14ms defines a PGOOD timeout
fault condition that triggers a hard reset if not masked in
I²C register bit SCR2[7]. When SCR2[7] is HIGH, PGOOD
remains in normal operation.
During a dynamic voltage slew, PGOOD is pulled LOW
unless bit 5 in the dynamic target voltage register for
each regulator is set HIGH. The status register PGSTAT
is unaffected by a dynamic voltage slew.
Undervoltage Detection
The LTC3589 undervoltage (UV) detection circuit will out-
put a fault condition, locking out regulator operation, until
V_IN reaches 2.7V. Once V_IN is above 2.7V the LTC3589 will
operate normally until V_IN drops to 2.55V (typical). When
Thermal Shutdown Fault and Warning
Similar to the V_IN undervoltage detection circuits the over-
temperature detection circuits check for warning and fault
levels. An overtemperature fault will initiate a fault induced
shutdown. An overtemperature warning sets register bit
IRQSTAT[6] and pulls the IRQ pin LOW.
IRQ Pin and IRQSTAT Status Register Function
The IRQ pin and IRQSTAT status register report PGOOD
timeout fault, V_IN undervoltage warning and fault, and
high temperature warning and fault. Table 15 shows the
meaning of the IRQSTAT read-only status register bits.
Table 15. IRQSTAT Read-Only Register Bit Definitions
IRQSTAT[BIT] VALUE SETTING
3
1 PGOOD Timeout Fault (PGOOD Low >
14ms)
4
1 V_IN Undervoltage Warning (V_IN < 2.9V)
5
1
V_IN Undervoltage Fault (V_IN < 2.6V)
6
1 Thermal Limit Warning (T_J > 130°C)
7
1 Thermal Limit Fault (T_J > 150°C)
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