DG-IRMCK203 Datasheet, PDF (9/67 Pages) International Rectifier – Application Developer’s Guide

IRMCK203 Application Developer’s Guide
BAUDSEL1
PIN 42
0 or low
0 or low
1 or high
1 or high
BAUDSEL0
PIN 30
0 or low
1 or high
0 or low
1 or high
Resulting BAUD Selection
19.2 K BAUD
38.4 K BAUD
57.6 K BAUD
1 MEG BAUD
Table 1. BAUD Selection Table
The RS-232 interface implements a byte serial physical layer in addition to an error checking protocol layer.
The coding of the bit-serial data is US ASCII, 8 data bits, 1 stop bit and no parity.
Table 2 describes the physical layer signals of the RS-232 interface.
Signal Name
TX
RX
Direction
Output
Input
Description
A bit-serial signal originated by the IRMCK203 in response to a
microprocessor-generated request.
Bit-serial data sent to the IRMCK203 by the microprocessor to interrogate
one of the Host Registers.
Table 2. External RS-232 Signal Description
2.3.2 SPI Interface
The SPI Interface is also a byte serial interface, but can operate at much greater transfer rates than the RS-232
interface. Bit rates of up to 8 MHz can be achieved. The SPI Interface performs a serial byte read and write in a "full
duplex" mode. Refer to the SPI Access documentation in Section 4.1.2 for the protocols required to access the Host
Registers, and the SPI timing section of the IRMCK203 datasheet for the physical layer specifications.
Table 3 describes the physical layer signals of the SPI interface.
Signal Name
SPICLK
SPIMOSI
SPIMISO
SPICSN
Direction
Input
Output
Input
Input
Description
Serial clock generated by the SPI master logic.
Serial data: Master Input and Slave Output.
Serial data: Master Output and Slave Input.
Chip Select signal. Used to qualify the SPICLK, SPIMISO and SPIMOSI
signals.
Table 3. External SPI I/F Signal Description
2.3.3 Host Parallel Interface
Designed to transfer bytes in a bit parallel fashion, this is the fastest interface of the three. The Host Parallel interface
is compatible with all popular microprocessors, including Motorola and Intel based bus protocols. Refer to the Parallel
Access documentation in Section 4.1.1 for the protocols required to access the Host Registers, and the Host Parallel
timing section of the IRMCK203 datasheet for the physical layer specifications.
Table 4 describes the physical layer signals of the Host Parallel interface.
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