DG-IRMCK203 Datasheet, PDF (43/67 Pages) International Rectifier – Application Developer’s Guide

IRMCK203 Application Developer’s Guide
Field
Name
DcBusMEnb
FltClr
Access Field Description
(R/W)
DC Bus monitor enable. 1 = Monitor DC bus voltage and generate
appropriate brake signal control and disable PWM output when
voltage fault conditions occur. GatekillFlt and OvrSpdFlt faults
cannot be disabled. DC bus voltage thresholds are as follows:
W Overvoltage – 410V
Brake On – 380V
Brake Off – 360V
Nominal – 310V
Undervoltage off – 140V
Undervoltage – 120V
This bit clears all active fault conditions. The user should monitor
the FaultStatus read register group to determine fault status and set
this bit to “1” to clear any faults that have occurred. A fault condition
W automatically clears the PwmEnbW and FocEnbW bits in the
SystemControl write register group. Note that this bit also directly
controls the output 2137 FLTCLR pin. After clearing a fault, the
user must explicitly set this bit to “0” to re-enable fault processing.
FaultControl Write Register Field Definitions
4.2.7 SystemConfig Register Group (Write Registers)
Byte
Offset
Bit Position
7
6
5
4
3
2
1
0
0x50
ExtCtrl
AdcIfbEnb Ramp
SPARE
Stop
SystemConfig Write Register Map
Field
Name
RampStop
AdcIfbEnb
ExtCtrl
Access Field Description
(R/W)
Selects the stopping mode:
W 0 - Configure for Coast stopping
1 - Configure for Ramp stopping
W Selects the current feedback mode:
0 - Selects IR2175 current feedback
1 - Selects Leg-Shunt current feedback
Setting this bit to “1” enables direct control of basic motor operation
W via the external User Interface pins. When this bit is “1”, the
FocEnbW and PwmEnbW bits in the SystemControl write register
group are ignored.
SystemConfig Write Register Field Definitions
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