DG-IRMCK203 Datasheet, PDF (60/67 Pages) International Rectifier – Application Developer’s Guide

IRMCK203 Application Developer’s Guide
PWM Operation
Referring to Figure 24, upon receiving the modulation index commands (U_Alpha and U_Beta) the sub-module
SVPWM_Tm starts its calculations at the rising edge of the PwmLoad signal. The SVPWM_Tm module implements
an algorithm that selects (based on sector determination) the active space vectors (V1 to V6) being used and calculates
the appropriate time duration (w.r.t. one PWM cycle) for each active vector. The appropriated zero vectors are also
being selected. The SVPWM_Tm module consumes 11 clock cycles typically and 35 clock cycles (worst case Tr) in
over modulation cases. At the falling edge of nSYNC, a new set of Space Vector times and vectors are readily
available for actual PWM generation (PhaseU, PhaseV, PhaseW) by sub module PwmGeneration. It is crucial to
trigger PwmLoad at least 35 clock cycles prior to the falling edge of nSYNC signal; otherwise new modulation
commands will not be implemented at the earliest PWM cycle.
Figure 24 (3-phase modulation) and Figure 25 (2-phase modulation) illustrates the PWM waveforms for a voltage
vector locates in sector I of the Space Vector plane (Figure 21). The gating pattern outputs (PWMUH … PWMWL)
include deadtime insertion (describe in later section).
Tr
nSYNC
PwmLoad
PhaseU
PhaseV
PhaseW
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
Td
Tpwm
Figure 24. 3-phase Space Vector PWM
Tr
nSYNC
PwmLoad
PhaseU
PhaseV
PhaseW
PWMUH
PWMUL
PWMVH
Td
PWMVL
PWMWH
PWMWL
Tpwm
Figure 25. 2-phase (6-step PWM) Space Vector PWM
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