DG-IRMCK203 Datasheet, PDF (33/67 Pages) International Rectifier – Application Developer’s Guide

IRMCK203 Application Developer’s Guide
4 Reference
4.1 Register Access
A host computer controls the IRMCK203 using its slave-mode Full-Duplex SPI port, a standard RS-232 port or a 8-bit
parallel port for connection to a microprocessor. All interfaces are always active and can be used interchangeably,
although not simultaneously. Control/status registers are mapped into a 128-byte address space.
4.1.1 Host Parallel Access
The IRMCK203 contains an address register that is updated with the Host Register address when HP_A = 1. After
each subsequent data byte is either read or written, the internal address register is incremented. The diagram below
shows that Data Bytes 0 to N would access register locations initially specified by the Address Byte. The Address
Bye with the HP_A signal can be asserted at any time.
Address Byte
HP_A = 1
Data Byte 0
HP_A = 0
…………….
HP_A = 0
Data Byte N
HP_A = 0
Host Parallel Data Transfer Format
4.1.2 SPI Register Access
When configured as an SPI device read only and read/write operations are performed using the following transfer
format:
Command Byte
Data Byte 0
…………….
Data Transfer Format
Data Byte N
Bit Position
7
6
5
4
3
2
1
0
Read
Only
Register Map Starting Address
Command Byte Format
Data transfers begin at the address specified in the command byte and proceed sequentially until the SPI transfer
completes. As in the Host Parallel Access, the internal address register is incremented after each SPI byte is
transferred. Note that accesses are read/write unless the “read only” bit is set.
4.1.3 RS-232 Register Access
The IRMCK203 includes an RS-232 interface channel that provides a direct connection to the host PC. The software
interface combines a basic "register map" control method with a simple communication protocol to accommodate
potential communication errors.
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