DG-IRMCK203 Datasheet, PDF (10/67 Pages) International Rectifier – Application Developer’s Guide

IRMCK203 Application Developer’s Guide
Signal Name
HP_nOE
HP_nWE
HP_D [7:0]
HP_A
Direction
Input
Input
Input/Output
Input
Description
When logic low, or 0, indicates the beginning of a parallel data transfer cycle.
When logic low, or 0, indicates that the data/address transfer cycle is a write cycle,
with data being sourced by the microprocessor. When high, the data cycle is a read
cycle, with data being sourced by the IRMCK203
An 8-bit wide data bus.
Address attribute signal. When high, or a logic 1, indicates that the data on the
HP_D[7:0] bus is a address to be loaded into the IRMCK203 address register.
Table 4. External Host Parallel I/F Signal Description
2.3.4 Synchronization of PWM Cycle to an External Microprocessor
A dedicated SYNC signal is provided on the IRMCK203 (pin 52) that allows synchronization of the internal
IRMCK203 logic to an external microprocessor. This synchronization is useful when external microprocessor
control loops are implemented. Also, an external trace buffer could be implemented to interrogate various nodes in
the IRMCK203 while the IRMCK203 is actively controlling the motor.
The SYNC signal has a long pulse width suitable to connect to an edge or level sensitive microprocessor interrupt
input pin. The low going edge of this pulse is an indication to the microprocessor that the IRMCK203 is starting a
new PWM cycle. Refer to the ADC System Level Timing section of the IRMCK203 datasheet for specific timing
information. Both the SPI and Host Parallel Interfaces are suitable for PWM Cycle and trace buffer synchronization.
The SYNC signal offers the microprocessor a timing window to access the entire Host Register set. The number of
SYNC pulses per PWM load can be configured using the support tools described in Section 3.
The SYNC pulse width is suitable for connecting opto-isolation circuitry between the IRMCK203 and the
microprocessor.
2.4 External Interfaces
This section describes the external interfaces supported by the IRMCK203 in addition to the host register interface
described in Section 2.3. These include the discrete I/O interface used for standalone operation and the analog I/O
interface provided for diagnostic purposes.
2.4.1 Discrete I/O External Interface
The discrete I/O external interface signals provide a means of controlling basic motor operation without using the host
register interface. In this mode of operation, the analog reference (described later in this section) is used to directly
control the target speed.
Figure 3 shows a schematic diagram of the discrete I/O signals. The signals are described in Table 5.
IRMCK203
Digital Control
IC
STARTSTOP
DIR
ESTOP
FLTCLR
FAULT
SYNC
Figure 3. Discrete I/O Signals
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