HMP8170 Datasheet, PDF (9/33 Pages) Intersil Corporation – NTSC/PAL Video Encoder

HMP8170, HMP8171, HMP8172, HMP8173
The MSBs of the accumulated phase value (PHINT) are
used to address the encoder’s sine look up ROM. The sine
values from the ROM are pre-scaled to generate the proper
levels for the various video standards. Prescaling outside the
CbCr data path minimizes color processing artifacts. The
HMP817x modulates the filtered 8:8:8 chrominance data
with the synthesized subcarrier.
The SCH phase is 0 degrees after reset but then changes
monotonically over time due to residue in the NCO. In an ideal
system, zero SCH phase would be maintained forever. In
reality, this is impossible to achieve due to pixel clock frequency
tolerances and digital rounding errors. When the PHINC source
is BT.656 data, the SCH phase reset should be disabled.
If enabled, the HMP817x resets the NCO periodically to
avoid an accumulation of SCH phase error. The reset occurs
at the beginning of each field to burst phase sequence. The
sequence repeats every 4 fields for NTSC or 8 fields for PAL.
Resetting the SCH phase every four fields (NTSC) or eight
fields (PAL) avoids the accumulation of SCH phase error at
the expense of requiring any NTSC/PAL decoder after the
encoder be able to handle very minor “jumps” (up to 2
degrees) in the SCH phase at the beginning of each four-
field or eight-field sequence. Most NTSC/PAL decoders are
able to handle this due to video editing requirements.
Composite Video Limiting
The HMP817x adds the luminance and modulated
chrominance together with the sync, color burst, and
optional blanking pedestal to form the composite video data.
If enabled in the video processing register, the encoder limits
the active video so that it is always greater than one-eighth
of full scale. This corresponds to approximately one-half the
sync height. This allows the generation of “safe” video in the
event non-standard YCbCr values are input to the device.
Controlled Edges
The NTSC and PAL video standards specify edge rates and
rise and fall times for portions of the video waveform. The
HMP817x automatically implements controlled edge rates
and rise and fall times on these edges:
1. Analog Horizontal Sync (Rising and Falling Edges)
2. Analog Vertical Sync Interval (Rising and Falling Edges)
3. Color Burst Envelope
4. Blanking of Analog Active Video
5. Closed Captioning Information
6. WSS Information
7. Teletext Information
“Sliced” VBI Data
The HMP817x generates three types of vertical blanking
interval data: closed captioning, widescreen signalling, and
teletext data. The data is generated on the scan lines
specified by the selected output video standard which are
enabled in the VBI data control register. During scan lines
with VBI data, the pixel inputs are ignored.
Closed Captioning (CC)
The HMP817x captioning data output includes clock run-in and
start bits followed by the captioning data. During closed
captioning encoding, the pixel inputs are ignored on the scan
lines containing captioning information.
The HMP817x has two 16-bit registers containing the
captioning information. Each 16-bit register is organized as
two cascaded 8-bit registers. One 16-bit register (caption 21)
is read out serially during line 18, 21 or 22; the other 16-bit
register (WSS 284) is read out serially during line 281, 284
or 335. The data registers are shifted out LSB first.
The captioning output level is 50 IRE for a logic 1 and 0 IRE
for a logic 0. All transitions between levels are controlled to
have a raised-cosine shape. The rise or fall time of any
transition is 240-288ns.
The caption data registers may be loaded via the I²C interface
or as BT.656 ancillary data. Table 6 illustrates the format of the
caption data as BT.656 ancillary data. The transfer should
occur only once per field before the start of the SAV sequence
of the line containing the captioning output.
When written via the I²C interface, the bytes may be written
in any order but both must be written within one frame time
for proper operation. If the registers are not updated, the
encoder resends the previously loaded values.
The HMP817x provides a write status bit for each captioning
line. The encoder clears the write status bit to ‘0’ when
captioning is enabled and both bytes of the captioning data
register have been written. The encoder sets the write status
bit to ‘1’ after it outputs the data, indicating the registers are
ready to receive new data.
Captioning information may be enabled for either line, both
lines, or no lines. The captioning modes are summarized in
Table 7.
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