HMP8170 Datasheet, PDF (18/33 Pages) Intersil Corporation – NTSC/PAL Video Encoder

HMP8170, HMP8171, HMP8172, HMP8173
BIT
NUMBER
7-5
4
3
2
1
0
FUNCTION
Reserved
Closed Caption
Line 21
Write Status
Closed Caption
Line 284
Write Status
WSS
Line 20
Write Status
WSS
Line 283
Write Status
Reserved
BIT
NUMBER
7
FUNCTION
Software Reset
6
General
Power Down
5
Power Down
NTSC/PAL 1
Output DAC
4
Power Down
NTSC/PAL 2
Output DAC
3
Power Down
Y Output DAC
2
Power Down
C Output DAC
1-0
Reserved
BIT
NUMBER
7-0
FUNCTION
Line 21 Caption
LSB Data
BIT
NUMBER
7-0
FUNCTION
Line 21 Caption
MSB Data
TABLE 22. HOST CONTROL REGISTER 1
SUB ADDRESS = 0E_H
DESCRIPTION
0 = Caption_21A and Caption_21B data registers contain unused data
1 = Data has been output, host processor may now write to the registers
RESET
STATE
000_B
1_B
0 = Caption_284A and Caption_284B data registers contain unused data
1_B
1 = Data has been output, host processor may now write to the registers
0 = WSS_20A, WSS_20B, CRC_20A, and CRC_20B data registers contain
1_B
unused data
1 = Data has been output, host processor may now write to the registers
0 = WSS_283A and WSS_283B data registers contain unused data
1_B
1 = Data has been output, host processor may now write to the registers
TABLE 23. HOST CONTROL REGISTER 2
SUB ADDRESS = 0F_H
DESCRIPTION
Setting this bit to “1” initiates a software reset. It is automatically reset to a “0” after the reset
sequence is complete.
This bit powers down all DAC outputs and most of the digital circuitry.
0 = Normal operation
1 = Power down mode
This bit powers down only the NTSC/PAL 1 DAC output.
0 = Normal operation
1 = Power down mode
This bit powers down only the NTSC/PAL 2 DAC output.
0 = Normal operation
1 = Power down mode
This bit powers down only the Y DAC output.
0 = Normal operation
1 = Power down mode
This bit powers down only the C DAC output.
0 = Normal operation
1 = Power down mode
TABLE 24. CLOSED CAPTION_21A DATA REGISTER
SUB ADDRESS = 10_H
DESCRIPTION
This register is cascaded with the closed caption_21B data register and they are read out
serially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. Bit D0 of the 21A
data register is shifted out first.
0_B
RESET
STATE
0_B
0_B
0_B
0_B
0_B
0_B
00_B
RESET
STATE
80_H
TABLE 25. CLOSED CAPTION_21B DATA REGISTER
SUB ADDRESS = 11_H
DESCRIPTION
This register is cascaded with the closed caption_21A data register and they are read out
serially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. Bit D0 of the 21A
data register is shifted out first.
RESET
STATE
80_H
18