HMP8170 Datasheet, PDF (5/33 Pages) Intersil Corporation – NTSC/PAL Video Encoder

HMP8170, HMP8171, HMP8172, HMP8173
CLK2
P8-P15 Cb 2 Y 2
Cr 2
Y3
Cb 4
Y4
"FF" "00" "00" EAV
"10" "80" "10"
BLANK
(OUTPUT)
FIGURE 3. PIXEL INPUT TIMING - BT.656
TABLE 3. BT.656 EAV AND SAV SEQUENCES
PIXEL INPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble Word 1
1
1
1
1
1
1
1
1
Preamble Word 2
0
0
0
0
0
0
0
0
Preamble Word 3
0
0
0
0
0
0
0
0
Status Word
1
F
V
H
P3
P2
P1
P0
NOTES:
F: 0 = Field 1; 1 = Field 2
V: 0 = Active Line; 1 = Vertical Blanking
H: 0 = Start Active Video; 1 = End Active Video
P3 - P0: Protection bits; Ignored
Video Timing Control
The pixel input data and the output video timing of the
HMP817x are at 50 or 59.94 fields per second interlaced.
The timing is controlled by the BLANK, HSYNC, VSYNC,
FIELD, and CLK2 pins.
HSYNC, VSYNC, and Field Timing
The leading edge of HSYNC indicates the beginning of a
horizontal sync interval. If HSYNC is an output, it is asserted
for about 4.7µs. If HSYNC is an input, it must be active for at
least two CLK2 periods. The width of the analog horizontal
sync tip is determined from the video standard and does not
depend on the width of HSYNC.
The leading edge of VSYNC indicates the beginning of a
vertical sync interval. If VSYNC is an output, it is asserted for
3 scan lines in (MM) NTSC and (M, N) PAL modes or 2.5
scan lines in (B, D, G, H, I, NC) PAL modes. If VSYNC is an
input, it must be asserted for at least two CLK2 periods.
When HSYNC and VSYNC are configured as outputs, their
leading edges will occur simultaneously at the start of an
odd field. At the start of an even field, the leading edge of
VSYNC occurs in the middle of the line.
When HSYNC and VSYNC are configured as inputs, the
HMP817x provides a programmable HSYNC window for
determining FIELD. The window is specified with respect to
the leading or trailing edge of VSYNC. The edge is selected
in the field control register. When HSYNC is found inside the
window, then the encoder sets FIELD to the value specified
in the field control register.
The HMP817x provides programmable timing for the
VSYNC input. At the active edge of VSYNC, the encoder
resets its vertical half-line counter to the value specified by
the field control register. This allows the input and output
syncs to be offset, although the data must still be aligned.
The FIELD signal is always an output and changes state
near each leading edge of VSYNC. The delay between the
syncs and FIELD depends on the encoder’s operating mode
as summarized in Table 4. In modes in which the encoder
uses CLK to gate its inputs and outputs, the FIELD signal
may be delayed 0-12 additional CLK2 periods.
TABLE 4. FIELD OUTPUT TIMING
OPERATING MODE
SYNC I/O BLANK I/O CLK2
DIRECTION DIRECTION DELAY
COMMENTS
Input
Input
148 FIELD lags VSYNC
switching from odd to
even.
FIELD lags the earlier
of VSYNC and HSYNC
when syncs are aligned
when switching from
even to odd.
Input
Output
138 FIELD lags VSYNC.
Output
Don’t Care 32
FIELD leads VSYNC.
Figure 4 illustrates the HSYNC, VSYNC, and FIELD general
timing for (M) NTSC and (M, N) PAL. Figure 5 illustrates the
general timing for (B, D, G, H, I, NC) PAL. In the figures, all
the signals are shown active low (their reset state), and
FIELD is low during odd fields.
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