HMP8170 Datasheet, PDF (20/33 Pages) Intersil Corporation – NTSC/PAL Video Encoder

HMP8170, HMP8171, HMP8172, HMP8173
BIT
NUMBER
FUNCTION
7-6
Reserved
5-0
Line 283
WSS CRC Data
TABLE 33. CRC_283 REGISTER
SUB ADDRESS = 19_H
DESCRIPTION
This register is read out serially after the 14 bits of NTSC WSS data, if WSS is enabled. It is
ignored during PAL WSS operation. Bit D0 is shifted out first.
RESET
STATE
00_B
111111_B
BIT
NUMBER
FUNCTION
7-0
LSB Assert BLANK
Output Signal
(Horizontal)
TABLE 34. START H_BLANK LOW REGISTER
SUB ADDRESS = 20_H
DESCRIPTION
This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020_H. This
register is ignored unless BLANK is configured as an output.
RESET
STATE
4A_H
TABLE 35. START H_BLANK HIGH REGISTER
BIT
NUMBER
FUNCTION
SUB ADDRESS = 21_H
DESCRIPTION
7-2
Reserved
1-0
MSB Assert BLANK This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit
Output Signal
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
(Horizontal)
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020_H. This
register is ignored unless BLANK is configured as an output.
RESET
STATE
000000_B
11_B
BIT
NUMBER
FUNCTION
7-0
Negate BLANK
Output Signal
(Horizontal)
TABLE 36. END H_BLANK REGISTER
SUB ADDRESS = 22_H
DESCRIPTION
This 8-bit register specifies the horizontal count (in 1x clock cycles) at which to start inputting
pixel data each scan line. The leading edge of HSYNC is count 000_H. This register is ignored
unless BLANK is configured as an output.
RESET
STATE
7A_H
TABLE 37. START V_BLANK LOW REGISTER
BIT
NUMBER
FUNCTION
SUB ADDRESS = 23_H
DESCRIPTION
7-0
LSB Assert BLANK This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
Output Signal
start_vertical_blank register. During normal operation, it specifies the line number (n) to start
(Vertical)
ignoring pixel input data (and what line number to start blanking the output video) each odd
field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000_H (note that this does not
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is
configured as an output.
RESET
STATE
03_H
20