HMP8170 Datasheet, PDF (19/33 Pages) Intersil Corporation – NTSC/PAL Video Encoder

HMP8170, HMP8171, HMP8172, HMP8173
BIT
NUMBER
7-0
FUNCTION
Line 284 Caption
LSB Data
BIT
NUMBER
7-0
FUNCTION
Line 284 Caption
MSB Data
BIT
NUMBER
7-0
FUNCTION
Line 20
WSS LSB Data
BIT
NUMBER
7-6
5-0
FUNCTION
Reserved
Line 20
WSS MSB Data
BIT
NUMBER
7-0
FUNCTION
Line 283
WSS LSB Data
BIT
NUMBER
7-6
5-0
FUNCTION
Reserved
Line 283
WSS MSB Data
BIT
NUMBER
7-6
5-0
FUNCTION
Reserved
Line 20
WSS CRC Data
TABLE 26. CLOSED CAPTION_284A DATA REGISTER
SUB ADDRESS = 12_H
DESCRIPTION
This register is cascaded with the closed caption_284B data register and they are read out
serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit D0 of the
284A data register is shifted out first.
RESET
STATE
80_H
TABLE 27. CLOSED CAPTION_284B DATA REGISTER
SUB ADDRESS = 13_H
DESCRIPTION
This register is cascaded with the closed caption_284A data register and they are read out
serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit D0 of the
284A data register is shifted out first.
RESET
STATE
80_H
TABLE 28. WSS_20A DATA REGISTER
SUB ADDRESS = 14_H
DESCRIPTION
This register is cascaded with the WSS_20B data register and they are read out serially as 14
bits during line 17, 20, or 23 if WSS is enabled. Bit D0 of the WSS_20A data register is shifted
out first.
RESET
STATE
00_H
TABLE 29. WSS_20B DATA REGISTER
SUB ADDRESS = 15_H
DESCRIPTION
This register is cascaded with the WSS_20A data register and they are read out serially as 14
bits during line 17, 20, or 23 if WSS is enabled. Bit D0 of the WSS_20A data register is shifted
out first.
RESET
STATE
00_B
000000_B
TABLE 30. WSS_283A DATA REGISTER
SUB ADDRESS = 16_H
DESCRIPTION
This register is cascaded with the WSS_283B data register and they are read out serially as
14 bits during line 280, 283, or 336 if WSS is enabled. Bit D0 of the WSS_283A data register
is shifted out first.
RESET
STATE
00_H
TABLE 31. WSS_283B DATA REGISTER
SUB ADDRESS = 17_H
DESCRIPTION
This register is cascaded with the WSS_283A data register and they are read out serially as
14 bits during line 280, 283, or 336 if WSS is enabled. Bit D0 of the WSS_283A data register
is shifted out first.
RESET
STATE
00_B
000000_B
TABLE 32. CRC_20 REGISTER
SUB ADDRESS = 18_H
DESCRIPTION
This register is read out serially after the 14 bits of NTSC WSS data, if WSS is enabled. It is
ignored during PAL WSS operation. Bit D0 is shifted out first.
RESET
STATE
00_B
111111_B
19