HMP8170 Datasheet, PDF (14/33 Pages) Intersil Corporation – NTSC/PAL Video Encoder

HMP8170, HMP8171, HMP8172, HMP8173
Composite + YUV Output Mode
The HMP8172/HMP8173 also provide composite with
component YUV output mode. When analog YUV video is
selected, the HMP817x scales the filtered YCbCr data to
match the levels required by its DACs. During the scaling,
values less than 16 are clamped to 16. The scaling factors
for Cb and Cr are the same, but the CbCr scaling factor is
different from the Y scaling factor. The encoder uses
different sets of scale factors for NTSC and PAL to
accommodate their different black levels.
The analog YUV outputs have a range of 0.3-1.0V with an
optional blanking pedestal. Composite sync information
(0.0-0.3V) may be optionally added to the Y output. VBI data
is included on the Y output. The HMP817x also generates
composite video when in YUV output mode. All four outputs
are time aligned. The output pin assignments are
summarized in Table 12.
Power Down Modes
To reduce power dissipation, any of the four output DACs
may be turned off. Each DAC has an independent enable bit.
Each output may be disabled in the host control register.
When the power down mode is enabled, all of the DACs and
internal voltage reference are powered down (forcing their
outputs to zero) and the data pipeline registers are disabled.
The host processor may still read from and write to the
internal control registers.
Host Interfaces
Reset
The HMP817x resets to its default operating mode on power
up, when the reset pin is asserted for at least four CLK
cycles, or when the software reset bit of the host control
register is set. During the reset cycle, the encoder returns its
internal registers to their reset state and deactivates the I²C
interface.
I²C Interface
The HMP817x provides a standard I²C interface and
supports fast-mode (up to 400Kbps) transfers. The device
acts as a slave for receiving and transmitting data only. It will
not respond to general calls or initiate a transfer. The
encoder’s slave address is either 0100 000x_B when the SA
input pin is low or 0100 001x_B when it is high. (The ‘x’ bit in
the address is the I²C read flag.)
The I²C interface consists of the SDA and SCL pins. When
the interface is not active, SCL and SDA must be pulled high
using external 4-6kΩ pull-up resistors. The I²C clock and
data timing is shown in Figures 10 and 11.
During I²C write cycles, the first data byte after the slave
address specifies the sub address, and is written into the
address register. Only the seven LSBs of the subaddress are
used; the MSB is ignored. Any remaining data bytes in the
I²C write cycle are written to the control registers, beginning
with the register specified by the address register. The 7-bit
address register is incremented after each data byte in the
I²C write cycle. Data written to reserved bits within registers
or reserved registers is ignored.
During I²C read cycles, data from the control register
specified by the address register is output. The address
register is incremented after each data byte in the I²C read
cycle. Reserved bits within registers return a value of “0”.
Reserved registers return a value of 00_H.
The HMP817x’s operating modes are determined by the
contents of its internal registers which are accessed via the
I²C interface. All internal registers may be written or read by
the host processor at any time. However, some of the bits
and words are read only or reserved and data written to
these bits is ignored.
Table 13 lists the HMP817x’s internal registers. Their bit
descriptions are listed in Tables 14 through 45.
TABLE 13. CONTROL REGISTER NAMES
SUB ADDRESS
(HEX)
CONTROL REGISTER
RESET
CONDITION
00
01
02
03
04
05
06
07
08-0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A-1F
20
21
22
23
24
25
26
27
28-2F
30-6A
6B-6F
70-7F
product ID
-
output format
00_H
input format
06_H
video processing
80_H
timing I/O 1
00_H
timing I/O 2
00_H
VBI data enable
00_H
VBI data input
00_H
reserved
-
host control 1
1E_H
host control 2
00_H
caption_21A
80_H
caption_21B
80_H
caption_284A
80_H
caption_284B
80_H
WSS_20A
00_H
WSS_20B
00_H
WSS_283A
00_H
WSS_283B
00_H
CRC_20
3F_H
CRC_283
3F_H
reserved
-
start h_blank low
4A_H
start h_blank high
03_H
end h_blank
7A_H
start v_blank low
03_H
start v_blank high
01_H
end v_blank
13_H
field control 1
00_H
field control 2
00_H
reserved
-
test and unused
-
phase increment
-
test and unused
-
14