HMP8170 Datasheet, PDF (10/33 Pages) Intersil Corporation – NTSC/PAL Video Encoder

HMP8170, HMP8171, HMP8172, HMP8173
TABLE 6. BT.656 ANCILLARY DATA FORMAT FOR CLOSED CAPTIONING DATA
PIXEL INPUT
P15
P14
P13
P12
P11
P10
Preamble 1
0
0
0
0
0
0
Preamble 2
1
1
1
1
1
1
Preamble 3
1
1
1
1
1
1
Data ID
ep#
ep
1
1
0
0
Data Block Number
ep#
ep
0
0
0
0
Data Word Count
ep#
ep
0
0
0
0
Caption Register Byte 3
ep#
ep
0
0
bit 15
bit 14
Caption Register Byte 1
ep#
ep
0
0
bit 11
bit 10
Caption Register Byte 1
ep#
ep
0
0
bit 7
bit 6
Caption Register Byte 0
ep#
ep
0
0
bit 3
bit 2
CRC
P14#
X
X
X
X
X
NOTES:
The even parity (EP and EP#) bits are ignored.
Line = Data Register Select: 0 = Line 21; 1 = 284.
X = Don’t Care.
P9
0
1
1
0
0
0
bit 13
bit 9
bit 5
bit 1
X
P8
0
1
1
Line
1
1
bit 12
bit 8
bit 4
bit 0
X
CLOSED
CAPTIONING
ENABLE BITS
00
01
10
11
TABLE 7. CLOSED CAPTIONING MODES
CAPTIONING REGISTER
284A
21A
OUTPUT LINE(S)
284B
21B
None
Ignored
Ignored
21 (NTSC)
18 (M PAL)
22 (Other PAL)
Ignored
Caption Data
284 (NTSC)
281 (M PAL)
335 (Other PAL)
Caption Data
Ignored
21, 284 (NTSC)
18, 281 (M PAL)
22, 335 (Other PAL)
Caption Data
Caption Data
WRITE STATUS BIT
284
Always 1
Always 1
21
Always 1
0 = Loaded
1 = Output
0 = Loaded
1 = Output
Always 1
0 = Loaded
1 = Output
0 = Loaded
1 = Output
Widescreen Signalling (WSS)
The HMP817x WSS data output includes clock run-in and
start codes followed by the WSS data. For NTSC operation,
the WSS data is followed by six bits of CRC data.
The HMP817x has two 14-bit registers containing the WSS
information and two 6-bit registers containing the WSS CRC
data. Each 14-bit register is organized as a 6-bit register
cascaded with an 8-bit one. One 14-bit register (WSS 20) is
read out serially during line 17, 20 or 23; the other 14-bit
register (caption 283) is read out serially during line 280, 283
or 336. The data registers are shifted out LSB first.
The WSS output level depends on the video format. For
NTSC operation (EIAJ CPX-1204), the WSS output level is 70
IRE for a logic 1 and 0 IRE for a logic 0. All transitions
between levels are controlled to have a raised-cosine shape
with a rise or fall time of 240ns. For PAL operation (ITU-R
BT.1119), the WSS output level is 71.5 IRE for a logic 1 and 0
IRE for a logic 0. All transitions between levels are controlled
to have a raised-cosine shape with a rise or fall time of 118ns.
The WSS data registers may be loaded via the I²C interface
or as BT.656 ancillary data. Table 8 illustrates the format of
the WSS data as BT.656 ancillary data. The transfer should
occur only once per field before the start of the SAV
sequence of the line containing the WSS output.
When written via the I²C interface, the bytes may be written
in any order but all three bytes of each enabled line must be
written within one frame time for proper operation. If the
registers are not updated, the encoder resends the
previously loaded values.
The HMP817x provides a write status bit for each WSS line.
The encoder clears the write status bit to ‘0’ when WSS is
enabled and all bytes of the WSS data register have been
written. The encoder sets the write status bit to ‘1’ after it
outputs the data, indicating the registers are ready to receive
new data.
WSS information may be enabled for either line, both lines,
or no lines. The WSS modes are summarized in Table 9.
10