HMP8170 Datasheet, PDF (24/33 Pages) Intersil Corporation – NTSC/PAL Video Encoder

HMP8170, HMP8171, HMP8172, HMP8173
Pin Descriptions (Continued)
PIN
NAME
PIN
NUMBER
INPUT/
OUTPUT
CLK
39
I/O
CLK2
41
I
SCL
18
I
SA
19
I
SDA
20
I/O
RESET
25
I
Y
3
O
C
7
O
NTSC/PAL 1
11
O
NTSC/PAL 2
15
O
VREF
61
I/O
FS_ADJUST
62
COMP 1
64
COMP 2
63
VAA
GND
DESCRIPTION
1x pixel clock input/output. As an input, this clock must be free-running and synchronous to
the clock signal on the CLK2 pin. As an output, this pin may drive a maximum of one LS TTL
load. CLK is generated by dividing CLK2 by two or four, depending on the mode. If not
driven, the circuit for this pin should include a 4-12kΩ pull up resistor connected to VAA.
2x pixel clock input. This clock must be a continuous, free-running clock.
I²C interface clock input. The circuit for this pin should include a 4-6kΩ pull-up resistor
connected to VAA.
I²C interface address select input.
I²C interface data input/output. The circuit for this pin should include a 4-6kΩ pull-up resistor
connected to VAA.
Reset control input. A logical zero for a minimum of four CLK cycles resets the device.
RESET must be a logical one for normal operation.
Luminance analog current output. This output contains luminance video, sync, blanking, and
information. In analog YUV or RGB output mode, an alternate signal is generated (see Table
12). It is capable of driving a 37.5Ω load. If not used, it should be connected to GND.
Chrominance analog current output. This output contains chrominance video, and blanking
information. In analog YUV or RGB output mode, an alternate signal is generated (see Table
12). It is capable of driving a 37.5Ω load. If not used, it should be connected to GND.
Composite video analog current output. This output contains composite video, sync,
blanking, and information. In analog YUV or RGB output mode, an alternate signal is
generated (see Table 12). It is capable of driving a 37.5Ω load. If not used, it should be
connected to GND.
Composite video analog current output. This output contains composite video, sync,
blanking, and information. In analog YUV or RGB output mode, an alternate signal is
generated (see Table 12). It is capable of driving a 37.5Ω load. If not used, it should be
connected to GND.
Voltage reference. An optional external 1.235V reference may be used to drive this pin. If
left floating, the internal voltage reference is used.
Full scale adjust control. A resistor (RSET) connected between this pin and GND sets the
full-scale output current of each of the DACs.
Compensation pin. A 0.1µF ceramic chip capacitor should be connected between this pin
and VAA, as close to the device as possible.
Compensation pin. A 0.1µF ceramic chip capacitor should be connected between this pin
and VAA as close to the device as possible.
+5V power. A 0.1µF ceramic capacitor, in parallel with a 0.01µF chip capacitor, should be
used between each group of VAA pins and GND. These should be as close to the device as
possible.
Ground
24