HMP8170 Datasheet, PDF (6/33 Pages) Intersil Corporation – NTSC/PAL Video Encoder

HMP8170, HMP8171, HMP8172, HMP8173
HSYNC
VSYNC
FIELD
FIGURE 4A. BEGINNING AN ODD FIELD
HSYNC
VSYNC
FIELD
FIGURE 4B. BEGINNING AN EVEN FIELD
FIGURE 4. HSYNC, VSYNC, AND FIELD TIMING FOR
(M) NTSC AND (M, N) PAL
HSYNC
VSYNC
FIELD
FIGURE 5A. BEGINNING AN ODD FIELD
HSYNC
VSYNC
FIELD
FIGURE 5B. BEGINNING AN EVEN FIELD
FIGURE 5. HSYNC, VSYNC, AND FIELD TIMING FOR
(B, D, G, H, I, NC) PAL
BLANK Timing
The encoder uses the HSYNC, VSYNC, FIELD signals to
generate a standard composite video waveform with no
active video (black burst). The signal includes only sync tips,
color burst, and optionally, a 7.5 IRE blanking setup. Based
on the BLANK signal, the encoder adds the pixel input data
to the video waveform.
The encoder ignores the pixel input data when BLANK is
asserted. Instead of the input data, the encoder generates
the blanking level. The encoder also ignores the pixel inputs
when generating VBI data on a specific line, even if BLANK
is negated.
There must be an even number of active and total pixels per
line. In the 8-bit YCbCr modes, the number of active and
total pixels per line must be a multiple of four. Note that if
BLANK is an output, half-line blanking on the output video
cannot be done.
The HMP817x never adds a 7.5 IRE blanking setup during
the active line time on scan lines 1-21 and 263-284 for (M)
NTSC, scan lines 523-18 and 260-281 for (M) PAL, and scan
lines 623-22 and 311-335 for (B, D, G, H, I, N) PAL, allowing
the generation of video test signals, timecode, and other
information by controlling the pixel inputs appropriately.
The relative timing of BLANK, HSYNC, and the output video
depends on the blanking and sync I/O directions. The typical
timing relation is shown in Figure 6. The delays which vary
with operating mode are indicated. The width of the
composite sync tip and the location and duration of the color
burst are fixed based on the video format.
.
COMPOSITE
VIDEO OUT
HSYNC
BLANK
DATA PIPE
DELAY
START H BLANK
SYNC DELAY
FIGURE 6. HSYNC, BLANK, AND OUTPUT VIDEO TIMING,
NORMAL MODE
When BLANK is an output, the encoder asserts it during the
inactive portions of active scan lines (horizontal blanking)
and for all of each inactive scan line (vertical blanking). The
inactive scan lines blanked each field are determined by the
start_v_blank and end_v_blank registers. The inactive
portion of active scan lines is determined by the
start_h_blank and end_h_blank registers.
The zero count for horizontal blanking is 32 CLK2 cycles
before the 50% point of the composite sync. From this zero
point, the HMP817x counts every other CLK2 cycle. When
the count reaches the value in the start_h_blank register, the
encoder negates BLANK. When the count reaches the value
in the end_h_blank register, BLANK is asserted. There may
be an additional 0-3 CLK2 delays in modes which use CLK.
The data pipeline delay through the HMP817x is 26 CLK2
cycles. In operating modes which use CLK to gate the
inputs into the encoder, the delay may be an additional 0-7
CLK2 cycles. The delay from BLANK to the start or end of
active video is an additional one-half CLK cycle when the
blank timing select bit is cleared. The active video may also
appear to end early or start late since the HMP817x
controls the blanking edge rates.
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