HMP8170 Datasheet, PDF (21/33 Pages) Intersil Corporation – NTSC/PAL Video Encoder

HMP8170, HMP8171, HMP8172, HMP8173
TABLE 38. START V_BLANK HIGH REGISTER
BIT
NUMBER
FUNCTION
SUB ADDRESS = 24_H
DESCRIPTION
RESET
STATE
7-1 Reserved
0000000_B
0
MSB Assert BLANK This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit
1_B
Output Signal
start_vertical_blank register. This register is ignored unless BLANK is configured as an output.
(Vertical)
BIT
NUMBER
FUNCTION
7-0
Negate BLANK
Output Signal
(Vertical)
TABLE 39. END V_BLANK REGISTER
SUB ADDRESS = 25_H
DESCRIPTION
During normal operation, this 8-bit register specifies the line number (n) to start inputting pixel
input data (and what line number to start generating active output video) each odd field; for
even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000_H (note that this does not
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is
configured as an output.
RESET
STATE
13_H
BIT
NUMBER
FUNCTION
7-0
Field Detect
Window Size Low
TABLE 40. FIELD CONTROL REGISTER 1
SUB ADDRESS = 26_H
DESCRIPTION
This 8-bit register is cascaded with Field Detect Window Size High to form a 9-bit Field Detect
Window Size value. The value specifies the number of 1x clock cycles in the detection window
before and after the selected edge of VSYNC. It may range from 0 to 511. If the leading edge
of HSYNC occurs within the window, it is the start of an odd or even field, as specified by the
FIELD Detect Select bit. This register is ignored unless HSYNC and VSYNC are configured
as inputs.
RESET
STATE
80_H
BIT
NUMBER
FUNCTION
7-4
Half Line Count
Reset Value
2
VSYNC Edge
Select
1
FIELD Detect
Select
0
Field Detect
Window Size High
TABLE 41. FIELD CONTROL REGISTER 2
SUB ADDRESS = 27_H
DESCRIPTION
These bits specify the value to load to the vertical half line counter when the selected edge of
VSYNC. The value is ignored when HSYNC and VSYNC are configured as outputs.
This bit specifies whether the encoder uses the leading or trailing edge of VSYNC to determine
the field and to reset the half line counter. It is ignored unless HSYNC and VSYNC are
configured as inputs.
0 = leading edge
1 = trailing edge
This bit specifies whether an odd or even field is starting when the leading edge of HSYNC
occurs within the FIELD Detect Window. It is ignored unless HSYNC and VSYNC are
configured as inputs.
0 = odd field
1 = even field
This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window
Size value. This bit is ignored unless HSYNC and VSYNC are configured as inputs.
RESET
STATE
00000_B
0_B
0_B
0_B
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