ISL70003SEH Datasheet, PDF (6/32 Pages) Intersil Corporation – Acceptance tested to 50krad

ISL70003SEH
Pin Descriptions (Continued)
PIN NUMBER
23, 28, 32, 37,
38, 43, 44, 49,
53, 58
29
30
31
24, 27, 33, 36,
39, 42, 45, 48,
54, 57
50
51
52
25, 26, 34, 35,
40, 41, 46, 47,
55, 56
59
60
61
62
63
64
PIN NAME ESD CIRCUIT
DESCRIPTION
PVINx
7
These pins are the power supply inputs to the corresponding internal power blocks. These pins must be
connected to a common power supply rail, which should fall in the range of 3V to 13.2V. Bypass these
pins directly to PGNDx with ceramic capacitors located as close as possible to the IC. When sinking
current or at a no load condition, the inductor valley current will be negative. During any time when the
inductor valley current is negative and the ISL70003 is exposed to a heavy ion environment, the abs
max PVIN voltage must be ≤13.7V.
SEL1
2
This pin is a logic-level disable (high) input working in conjunction with SEL2. These pins form a two-bit
logic input that set the number of active power blocks. This allows the ISL70003SEH current capability
to be tailored to the load current level the application requires and achieve the highest possible
efficiency.
SEL2
2
This pin is a logic-level disable input. Pulling this pin high inhibits pulses on the LXx outputs. See
description of Pin 29, SEL1, for more information.
DE
2
The DE pin enables or disables Diode Emulation. When it is HIGH, diode emulation is allowed.
Otherwise, continuous conduction mode is forced.
LXx
These pins are the switch node connections to the internal power blocks and should be connected to
the output filter inductor. Internally, these pins are connected to the synchronous MOSFET power
switches.
NC/HS
N/A This is a No Connect pin that is not connected to anything internally. In the R64.C package (heatsink
option) this pin is electrically connected to the heatsink on the underside of the package. Connect this
pin and/or the heatsink to a thermal plane.
IMON
1
IMON is a current source output that is proportional to the sensed current through the regulator. If not
used it is recommended to tie IMON to VREFA. It is also acceptable to tie IMON to GND through a
resistor.
SGND
1
This pin is connected to an internal metal trace that serves as a noise shield. Connect this pin to the
PCB ground plane.
PGNDx
7
These pins are the power grounds associated with the corresponding internal power blocks. Connect
these pins directly to the PCB ground plane. These pins should also connect to the negative terminals
of the input and output capacitors. The package lid is internally connected to PGNDx
OCSETA
3
This pin is the redundant output overcurrent set input. Connect a resistor from this pin to the PCB
ground plane to set the output overcurrent threshold.
OCSETB
3
This pin is the primary output overcurrent set input. Connect a resistor from this pin to the PCB ground
plane to set the output overcurrent threshold.
BUFIN+
1
This pin is the input to the internal unity gain buffer amplifier. For DDR memory power applications,
connect the VTT voltage to this pin.
BUFIN-
1
This pin is the inverting input to the buffer amplifier. For DDR memory power applications, connect
BUFOUT to this pin. Bypass this pin to the PCB ground plane with a 0.1µF ceramic capacitor.
BUFOUT
3
This pin is the output of the buffer amplifier. In DDR power applications, connect this pin to the
reference input of the DDR memory. The buffer needs a minimum of 1.0µF load capacitor for stability.
REF
1
This pin is the output of the internal reference voltage. Bypass this pin to the PCB ground plane with a
220nF ceramic capacitor located as close as possible to the IC. The bypass capacitor is needed to
mitigate SEE.
VREFA
PIN #
AGND
CIRCUIT 1
VREFD
PIN #
DGND
CIRCUIT 2
PIN #
7V
CLAMP
AGND
CIRCUIT 3
PIN #
7V
CLAMP
DGND
CIRCUIT 4
AVDD
12V
CLAMP
AGND
CIRCUIT 5
PIN #
12V
CLAMP
DGND
CIRCUIT 6
PVINx
12V
CLAMP
PGNDx
CIRCUIT 7
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6
FN8604.5
May 12, 2016