ISL70003SEH Datasheet, PDF(19/32 Page) Intersil Corporation

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ISL70003SEH Datasheet, PDF (19/32 Pages) Intersil Corporation – Acceptance tested to 50krad

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ISL70003SEH

Specificationsâ table on page 11. If the feedback voltage

exceeds the typical rising limit of 111% of the reference voltage,

the PGOOD pin pulls low. The PGOOD pin continues to pull low

until the feedback voltage falls to a typical of 107.5% of the

reference voltage. If the feedback voltage drops below a typical

of 89% of the reference voltage, the PGOOD pin pulls low. The

PGOOD pin continues to pull low until the feedback voltage rises

to a typical 92.5% of the reference voltage. The PGOOD pin then

releases and signals the return of the output voltage within the

power-good window

0.666V

PGOOD

0.534V

COUNTER/

POR/ ON-OFF

CONTROL

ISEN

OCP

UVP

OCSETB

0.45V

ISEN

OCP

OCSETA

FIGURE 40. POWER-GOOD AND PROTECTION CIRCUITRY

Undervoltage Protection

A hysteretic comparator monitors the FB pin of the regulator. The

feedback voltage is compared to an undervoltage threshold that

is a fixed percentage of the reference voltage, typically 75%.

Once the comparator trips, indicating a valid undervoltage

condition, an undervoltage counter increments. The counter is

reset if the feedback voltage rises back above the undervoltage

threshold plus a specified amount of hysteresis outlined in the

âElectrical Specificationsâ table on page 11. If there are 4

consecutive undervoltage detections the counter will overflow

and the undervoltage protection logic shuts down the regulator,

pulling PGOOD low.

After the regulator shuts down, it enters a delay interval,

approximately equivalent to 512 clock cycles plus 1 soft-start

intervals, allowing the device to cool. The undervoltage counter is

reset entering the delay interval. The protection logic initiates a

normal soft-start once the delay interval ends. If the output

successfully soft-starts, the power-good signal goes high and

normal operation continues. If undervoltage conditions continue

to exist during the soft-start interval, the undervoltage counter

must overflow before the regulator shuts down again. This hiccup

mode continues indefinitely until the output soft-starts

successfully.

Overcurrent Protection

A pilot device integrated into the PMOS transistor of Power Blocks

5 and 6 sample the current each cycle. This current feedback is

scaled and compared to an overcurrent threshold based on the

resistor value tied from pins OCSETA and OCSETB to AGND.

Upon detection of an overcurrent condition, the upper MOSFET

will be immediately turned off and will not be turned on again

until the next switching cycle. Upon detection of the initial

overcurrent condition, the overcurrent fault counter is set to 1. If,

on the subsequent cycle, another overcurrent condition is

detected, the OC fault counter will increment, however, if the

sampled current falls below the threshold the counter is reset. If

there are 4 sequential OC fault detections, the counter will

overflow and the regulator will be shutdown under an overcurrent

fault condition, pulling PGOOD low.

ÏÏ¬

LOAD CURRENT, 5A/DIV

Ïµ

Ï´

0Ï³A

Ï²

OUTPUT VOLTAGE, 1V/DIV

Ï±

Ï°

0Ï¯V

Ï®

SOFT-START VOLTAGE, 1V/DIV

0Ï¬V

5ms/DIV

FIGURE 1. OVERCURRENT BEHAVIOR IN HICCUP MODE

After the regulator shuts down, it enters a delay interval, allowing

the device to cool. The delay interval is approximately equal to

512 clock cycles plus 1 soft-start intervals. The overcurrent

counter is reset entering the delay interval. The protection logic

initiates a normal soft-start once the delay interval ends. If the

output successfully soft-starts, the power-good signal goes high

and normal operation continues. If overcurrent conditions

continue to exist during the soft-start interval, the overcurrent

counter must overflow before the regulator shutdowns the output

again. This hiccup mode continues indefinitely until the output

soft-starts successfully (see Figure 1).

Application Information

Voltage Feed-forward

Feed-forward is used to maintain a constant modulator gain and

achieve optimum loop response over a wide input voltage range.

A resistor from PVINx to RTCT and a capacitor from RTCT to

PGNDx are used to adjust the amplitude of the sawtooth ramp

proportional to the input voltage. The capacitor value must be

chosen so that it is large enough for mitigation of single event

transients but low enough for the internal MOSFET device to pull

the pin to ground. The following table gives the recommended

values for RT and CT for a given switching frequency. These

values will achieve a constant modulator gain across the

complete input voltage range.

FSEL STATE

fSW (kHz)

500

300

RT (kÎ©)

CT (pF)

370

MODULATOR

GAIN (TYP)

4.8

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May 12, 2016

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