ISL70003SEH Datasheet, PDF (22/32 Pages) Intersil Corporation – Acceptance tested to 50krad

ISL70003SEH
low-side MOSFET to turn on and sink the necessary current
needed to properly regulate the output voltage. The same
mechanism allows the converter to properly regulate the output
voltage when starting into a prebiased condition where the
prebias level is greater than the desired output voltage.
LXx
UGATE
LGATE
I_L
FIGURE 44. DIODE EMULATION
The DE pin is not intended to actively change states while the
regulator is operating. If any part of the inductor current is below
zero and the DE pin changes state there will be a glitch on the
output voltage. However, if the state of the DE pin changes state
when the inductor current is positive, no change in the operation
of the regulator will be seen.
DDR Application
High through put Double Data Rate (DDR) memory ICs are
replacing traditional memory ICs in space applications. A novel
feature associated with this type of memory are the referencing
and data bus termination techniques. These techniques employ
a reference voltage, V_REF, that tracks the center point of V_DDQ
and V_SS voltages, and an additional V_TT power source where all
terminating resistors are connected. Despite the additional
power source, the overall memory power consumption is reduced
compared to traditional termination.
The added power source has a cluster of requirements that
should be observed and considered. Due to the reduced
differential thresholds of DDR memory, the termination power
supply voltage, V_TT, closely tracks V_DDQ/2 voltage.
Another very important feature of the termination power supply
is the capability to operate at equal efficiency in sourcing and
sinking modes. The V_TT supply regulates the output voltage with
the same degree of precision when current is flowing from the
supply to the load, and when the current is diverted back from
the load into the power supply.
The ISL70003SEH regulator possesses several important
enhancements that allow reconfiguration for DDR memory
applications. Two ISL70003SEH ICs will provide all three voltages
required in a DDR memory compliant system.
DDR Configuration
V_DDQ
R_T1
FB
R_{B1 NI}
ISL70003SEH 1/2
ERROR
- ^AMPLIFIER
+
V_DDQ
R_T1
REF
V_REF
V_IN
PVIN_x
LX_x ^LO
PGND_x
V_DDQ
C_O1
R_B1
V_TT
NI
R_T2
FB
R_B2
B⁺
V_DDQ
B^-
R
ISL70003SEH 2/2
ERROR
+ ^AMPLIFIER
-
BUFFER
+ ^AMPLIFIER
-
OUTB
R
V_IN
PVIN_x
LX_x ^LO
PGND_x
V_TT
C_O2
V_REF
C_O3
FIGURE 45. SIMPLIFIED DDR APPLICATION SCHEMATIC
In the DDR application presented in Figure 45, an independent
architecture is implemented to generate the voltages needed for
DDR memory applications. Consequently, both V_DDQ and V_TT are
derived independently from the main power source. The first
regulator supplies the 2.5V for the V_DDQ voltage. The output
voltage is set by external dividers R_T1 and R_B1. The second
regulator generates the V_TT rail typically = V_DDQ/2. The resistor
divider network R_T2 and R_B2 are used to set the output voltage to
1.25V. The V_DDQ rail has an additional voltage divider network
consisting of R_T1 and R_B1, the midpoint is connected to the
noninverting input pin of the V_TT regulator’s error amplifier (NI),
effectively providing a tracking function for the V_TT voltage.
The noninverting input of the buffer amplifier is connected to the
center point of the external R/R divider from the VDDQ output.
The output of the buffer is tied back to the inverting input for
unity gain configuration. The buffer output voltage serves as a
1.25V reference (VREF) for the DDR memory chips. Sourcing
capability of the buffer amplifier is 10mA typical (20mA max)
and needs a minimum of 1µF load capacitance for stability.
Diode emulation mode of operation must be disabled on the V_TT
regulator to allow sinking capability. In the event both channels
are enabled simultaneously, the soft-start capacitor on the VDDQ
regulator should be two to three times larger than the soft-start
capacitor on the V_TT regulator. This allows the VDDQ regulator
voltage to be the lowest input into the error amplifier of the V_TT
regulator and dominate the soft-start ramp. However, if the V_TT
regulator is enabled later than the VDDQ, the soft-start capacitor
can be any value based on design goals.
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FN8604.5
May 12, 2016