ISL70003SEH Datasheet, PDF (26/32 Pages) Intersil Corporation – Acceptance tested to 50krad

ISL70003SEH
PCB Design
PCB design is critical to high-frequency switching regulator
performance. Careful component placement and trace routing
are necessary to reduce voltage spikes and minimize
undesirable voltage drops. Selection of a suitable thermal
interface material is also required for optimum heat dissipation
and to provide lead strain relief.
PCB Plane Allocation
A minimum of four layers of two ounce copper are
recommended. Layer 2 should be a dedicated ground plane with
all critical component ground connections made with vias to this
layer. Layer 3 should be a dedicated power plane split between
the input and output power rails. Layers 1 and 4 should be used
primarily for signals, but can also provide additional power and
ground islands as required.
PCB Component Placement
Components should be placed as close as possible to the IC to
minimize stray inductance and resistance. Prioritize the
placement of bypass capacitors on the pins of the IC in the order
shown: REF, SS, AVDD, DVDD, PVINx (high-frequency capacitors),
EN, PGOOD, PVINx (bulk capacitors).
Locate the output voltage resistive divider as close as possible to
the FB pin of the IC. The top leg of the divider should connect
directly to the output of the inductor via a kelvin trace and the
bottom leg of the divider should connect directly to AGND. This
AGND connection should also be a kelvin trace connected to the
closest ground to the inductor output. The junction of the
resistive divider should connect directly to the FB pin.
If desired place a Schottky clamp diode as close as possible to
the LXx and PGNDx pins of the IC. A small series R-C snubber
connected from the LXx pins to the PGNDx pins may be used to
damp high-frequency ringing on the LXx pins if desired.
ERROR
AMPLIFIER
-
+
LXx
3A
PGNDx
FB
NI
L_OUT
R_S
C_S
REF
C_REF
C_OUT
V_OUT
R_T
R_B
FIGURE 50. SCHOTTKY DIODE AND R-C SNUBBER
LX Connection
Use a small island of copper to connect the LXx pins of the IC to
the output inductor on layers 1 and 4. Void the copper on layers 2
and 3 adjacent to the island to minimize capacitive coupling to
the power and ground planes. Place most of the island on layer 4
to minimize the amount of copper that must be voided from the
ground plane (layer 2).
Keep all other signal traces as short as possible.
Thermal Management for Ceramic Package
For optimum thermal performance, place a pattern of vias on the
top layer of the PCB directly underneath the IC. Connect the vias
to the plane which serves as a heatsink. To ensure good thermal
contact, thermal interface material such as a Sil-Pad or thermally
conductive epoxy should be used to fill the gap between the vias
and the bottom of the IC of the ceramic package.
Lead Strain Relief
The package leads protrude from the bottom of the package and
the leads need forming to provide strain relief. On the ceramic
bottom package R64.A, the Sil-pad or epoxy maybe be used to fill
the gap left between the PCB board and the bottom of the
package when lead forming is completed. On the heatsink option
of the package R64.C, the lead forming should be made so that
the bottom of the heatsink and the formed leads are flush.
Heatsink Mounting Guidelines
The R64.C package option has a heatsink mounted on the
underside of the package. The following JESD-51x series
guidelines may be used to mount the package:
1. Place a thermal land on the PCB under the heatsink.
2. The land should be approximately the same size as to 1mm
larger than the 10.16x10.16mm heatsink.
3. Place an array of thermal vias below the thermal land.
- Via array size: ~9x9 = 81 thermal vias.
- Via diameter: ~0.3mm drill diameter with plated copper on
the inside of each via.
- Via pitch: ~1.2mm.
- Vias should drop to and contact as much metal area as
feasible to provide the best thermal path.
Heatsink Electrical Potential
The heatsink is connected to pin 50 within the package; thus the
PCB design and potential applied to pin 50 will therefore define
the heatsink potential.
Heatsink Mounting Materials
In the case of electrically conductive mounting methods
(conductive epoxy, solder, etc) the thermal land, vias and
connected plane(s) below must be the same potential as pin 50.
In the case of electrically non-conductive mounting methods
(non-conductive epoxy), the heatsink and pin 50 could have
different electrical potential than the thermal land, vias and
connected plane(s) below.
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FN8604.5
May 12, 2016