ISL70003SEH Datasheet, PDF (5/32 Pages) Intersil Corporation – Acceptance tested to 50krad

ISL70003SEH
Pin Descriptions
PIN NUMBER PIN NAME ESD CIRCUIT
DESCRIPTION
1
NI
1
This pin is the non-inverting input to the internal error amplifier. Connect this pin to the REF pin for
typical applications or the BUFOUT pin for DDR memory power applications.
2
FB
1
This pin is the inverting input to the internal error amplifier. An external type III compensation network
should be connected between this pin and the VERR pin. The connection between the FB resistor divider
and the output inductor should be a Kelvin connection to optimize performance.
3
VERR
1
This pin is the output of the internal error amplifier. An external compensation network should be
connected between this pin and the FB pin.
4
POR_VIN
1
This pin is the power-on reset input to the IC. This is a comparator-type input with a rising threshold of
0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND
with a 10nF ceramic capacitor to mitigate SEE.
5
VREFA
3
This pin is the output of the internal linear regulator and the bias supply input to the internal analog
control circuitry. Locally filter this pin to AGND using a 0.47µF ceramic capacitor as close as possible to
the IC.
6
AVDD
5
This pin provides the supply for internal linear regulator of the ISL70003SEH. The supply to AVDD
should be locally bypassed using a ceramic capacitor. Tie AVDD to the PVINx pins.
7
AGND
1, 3
This pin is the analog ground associated with the internal analog control circuitry. Connect this pin
directly to the PCB ground plane.
8
DGND
2, 4
This pin is the ground associated with the internal digital control circuitry. Connect this pin directly to
the PCB ground plane.
9
VREF_OUTS
4
This pin is the output of the internal linear regulator and the supply input to the internal reference
circuit. Locally filter this pin to AGND using a 0.47µF ceramic capacitor as close as possible to the IC.
10
DVDD
6
This pin provides the supply for the internal linear regulator of the ISL70003SEH. The supply to DVDD
should be locally bypassed using a ceramic capacitor. Tie DVDD to the PVINx pin.
11
VREFD
4
This pin is the output of the internal linear regulator and the bias supply input to the internal digital
control circuitry. Locally filter this pin to DGND using a 0.47µF ceramic capacitor as close as possible
to the IC.
12
ENABLE
6
This pin is a logic-level enable input. Pulling this pin low powers down the chip by placing it into a very
low power sleep mode.
13
RT/CT
6
A resistor to VIN and a capacitor to GND provide feed-forward to keep a constant modulator gain of 4.8
as VIN varies.
14
FSEL
2
This pin is the oscillator frequency select input. Tie this pin to 5V to select a 300kHz nominal oscillator
frequency. Tie this pin to the PCB ground plane to select a 500kHz nominal oscillator frequency.
15
SYNC
2
This pin is the frequency synchronization input to the IC. This pin should be tied to GND to free-run from
the internal oscillator or connected to an external clock for external frequency synchronization.
16
SS_CAP
2
This pin is the soft-start input. Connect a ceramic capacitor from this pin to the PCB ground plane to set
the soft-start output ramp time in accordance with Equation 1:
t_SS = C_SS  V_REF  I_SS
(EQ. 1)
where:
t_SS = soft-start output ramp time
C_SS = soft-start capacitance
V_REF = reference voltage (0.6V typical)
I_SS = soft-start charging current (23µA typical)
Soft-start time is adjustable from approximately 2ms to 200ms. The range of the soft-start capacitor
should be 82nF to 8.2µF, inclusive.
17, 18, 19, 20, 21 GND
2
Connect this pin to the PCB ground plane.
22
PGOOD
6
This pin is the power-good output. This pin is an open-drain logic output that is pulled to DGND when
the output voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage
from 0V to 13.2V, independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is
recommended. Bypass this pin to the PCB ground plane with a 10nF ceramic capacitor to mitigate SEE.
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5
FN8604.5
May 12, 2016