ISL70003SEH Datasheet, PDF (18/32 Pages) Intersil Corporation – Acceptance tested to 50krad

ISL70003SEH
V_R = 0.6V
I_POR = 12µA
C_POR = 10nF
V_IN
PVINx
POR
LOGIC
POR
COMPARATOR
+
- ^VR
V_IN
R₁
POR
C_POR R₂
I_POR
FIGURE 38. POR CIRCUIT
Equation 2 defines the relationship between the resistor divider,
sink current and POR rising level (V_PORR).
V_PORR = V_R  1 + _R-^R----¹²- + I_POR  R₁
(EQ. 2)
Once the voltage at the POR pin reaches the enable threshold,
the I_POR current sink turns off.
With the part enabled and the I_POR current sink off, the falling level
(V_PORF) is set by the resistor divider network and is defined by
Equation 3.
V_PORF = V_R  1 + _R-^R----¹²-
(EQ. 3)
The difference between the POR rising and falling levels provides
adjustable hysteresis so that noise on V_IN does not interfere with
the enabling or disabling of the regulator.
Soft -Start
The ISL70003SEH soft-start function uses an internal current
source and an external capacitor to reduce stresses and surge
current during start-up.
Once the POR and enable circuits are satisfied, the regulator
waits 32 clock cycles and then initiates a soft-start. Figure 39
shows that the soft-start circuit clamps the error amplifier
reference voltage to the voltage on an external soft-start
capacitor connected to the SS pin. The soft-start capacitor is
charged by an internal I_SS current source. As the soft-start
capacitor is charged, the output voltage slowly ramps to the set
point determined by the reference voltage and the feedback
network. Once the voltage on the SS pin is equal to the internal
reference voltage, the soft-start interval is complete. The
soft-start output ramp interval is defined in Equation 4 and is
adjustable from approximately 2ms to 200ms. The value of the
soft-start capacitor, C_SS, should range from 82nF to 8.2µF,
inclusive. The peak in-rush current can be computed from
Equation 5. The soft-start interval should be selected long
enough to insure that the peak in-rush current plus the peak
output load current does not exceed the overcurrent trip level of
the regulator.
t_SS = C_SS  ^V----_I-^R-_S---^ES----^F-
(EQ. 4)
I_INRUSH = C_OUT  ^V----_t-^O-_S---^U-_S---^T--
(EQ. 5)
The soft-start capacitor is immediately discharged by a 3.0Ω
resistor whenever POR conditions are not met or EN is pulled low.
The soft-start discharge time is equal to 256 clock cycles.
V_REF = 0.6V
I_SS = 23µA
R_D = 2.2Ω
V_OUT
R_T
FB
PWM
LOGIC
ERROR
AMPLIFIER
SS
-
+
+ _{VREF RD}
NI
I_SS
R_B
C_SS
V_REF
REF
C_REF
FIGURE 39. SOFT-START CIRCUIT
Power-Good
A power-good indicator is the final step of initialization. After a
successful soft-start, the PGOOD pin releases and the voltage
rises with an external pull-up resistor. The power-good signal
transitions low immediately when the EN pin is pulled low.
The PGOOD pin is an open-drain logic output and can be pulled
up to any voltage from 0V to 13.2V. The pull-up resistor should
have a nominal value from 1kΩ to 10kΩ. The PGOOD pin should
be bypassed to DGND with a 10nF ceramic capacitor to mitigate
SEE.
Fault Monitoring and Protection
The ISL70003SEH actively monitors the output voltage and
current to detect fault conditions. Fault conditions trigger
protective measures to prevent damage to the regulator and the
external load device. One common power-good indication signal
is provided for linking to external system monitors. The
schematic in Figure 40 on page 19 outlines the interaction
between the fault monitors and the power-good signal.
Undervoltage and Overvoltage Monitor
The power-good pin (PGOOD) is an open-drain logic output which
indicates that the converter is operating properly and the output
voltage is within a set window. The Undervoltage (UV) and
Overvoltage (OV) comparators create the output voltage window.
The power-good circuitry monitors the FB pin and compares it to
the rising and falling thresholds shown in the “Electrical
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FN8604.5
May 12, 2016