ISL70003SEH Datasheet, PDF (25/32 Pages) Intersil Corporation – Acceptance tested to 50krad

ISL70003SEH
Feedback Compensation
Figure 48 highlights the voltage-mode control loop for a
synchronous rectified buck converter. The output voltage (V_OUT)
is regulated to the reference voltage level. The error amplifier
output (V_EA) is compared with the oscillator (OSC) triangular
wave to provide a Pulse-Width Modulated (PWM) wave with an
amplitude of V_IN at the PHASE node. The PWM wave is smoothed
by the output filter (L_O and C_O).
OSC
PWM
COMPARATOR
Δ V_OSC
+-
DRIVER
DRIVER
V_IN
L_O
PHASE _CO
V_OUT
Z_FB
V_EA
+-
Z_IN
ERROR ^REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C₁
C₂
R₂
Z_FB
V_OUT
Z_IN
C_{3 R3}
VERR
-
+
R₁
FB
R₄
REFERENCE
VOUT
=
0.6
Â¥



1
+
RR-----14--_{}
FIGURE 48. VOLTAGE-MODE BUCK CONVERTER COMPENSATION
The modulator transfer function is the small-signal transfer
function of V_OUT/V_EA. This function is dominated by a DC Gain and
the output filter (L_O and C_O), with a double pole break frequency at
f_LC and a zero at f_ESR. The DC gain of the modulator is simply the
input voltage (V_IN) divided by the peak-to-peak oscillator voltage
ΔV_OSC. The ISL70003SEH incorporates a feed-forward loop that
accounts for changes in the input voltage. This maintains a
constant modulator gain of 5, typical.
Modulator Break Frequency Equations
fLC=
-------------------------1----------------------------
2 x LO x CO
fESR= _{2------}-------x-------E-----S1-----R--------x-------C-----O---
(EQ. 19)
The compensation network consists of the error amplifier and
the impedance networks Z_IN and Z_FB. The goal of the
compensation network is to provide a closed loop transfer
function with the highest 0dB crossing frequency (f_0dB) and
adequate phase margin. Phase margin is the difference between
the closed loop phase at f_0dB and 180°.
100
f_Z1 f_Z2 f_P1 f_P2
80
60
OPEN LOOP
ERROR AMP GAIN
40 _20LOG
20 ^(R2^/R1⁾
20LOG
0
(V_IN/DV_OSC)
-20
MODULATOR
GAIN
-40
-60 ₁₀
100
f_LC
f_ESR
1k
10k 100k
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 49. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Equation 20 relates the compensation network’s poles, zeros
and gain to the components (R₁ , R₂, R₃, C₁ , C₂ and C₃) in
Figure 48. Use these guidelines for locating the poles and zeros
of the compensation network:
1. Pick Gain (R₂/R₁) for desired converter bandwidth.
2. Place 1^st Zero Below Filter’s Double Pole (~75% F_LC).
3. Place 2^nd Zero at Filter’s Double Pole.
4. Place 1^st Pole at the ESR Zero.
5. Place 2^nd Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
f_Z1 = -2-----_-------x-------R--1---₂-------x-------C-----₂--
f_Z2 = -2-----_-------x-------_---R------₁------1+-------R-----₃-----_------x------C-----₃---
f_P1
=
-----------------------------------1--------------------------------------
2
x
R₂
x



-CC-----¹¹------+-x------CC-----₂₂-- _{}
f_P2 = -2-----_-------x-------R--1---₃-------x-------C-----₃--
(EQ. 20)
Figure 49 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not shown
in Figure 49. Using the guidelines provided should give a
Compensation Gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at f_P2 with the capabilities of the error
amplifier. The Closed Loop Gain is constructed on the graph of
Figure 49 by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to multiplying the
modulator transfer function to the compensation transfer
function and plotting the gain. The compensation gain uses
external impedance networks Z_FB and Z_IN to provide a stable,
high bandwidth (BW) overall loop. A stable control loop has a
gain crossing with -20dB/decade slope and a phase margin
greater than +45°. Include worst case component variations
when determining phase margin. A more detailed explanation of
voltage mode control of a buck regulator can be found in Tech
Brief TB417, entitled “Designing Stable Compensation Networks
for Single Phase Voltage Mode Buck Regulators”.
Submit Document Feedback ₂₅
FN8604.5
May 12, 2016