ISL70003SEH Datasheet, PDF (1/32 Pages) Intersil Corporation – Acceptance tested to 50krad

DATASHEET
Radiation Hardened and SEE Hardened 3V to 13.2V, 6A
Buck Regulator
ISL70003SEH
The ISL70003SEH is a radiation and SEE hardened
synchronous buck regulator capable of operating over an
input voltage range of 3.0V to 13.2V. With integrated
MOSFETs, this highly efficient single chip power solution
provides a tightly regulated output voltage that is externally
adjustable from 0.6V to ~90% of the input voltage.
Continuous output load current capability is 6A for
T_J ≤+125°C and 3A for T_J ≤ +150°C.
The ISL70003SEH uses voltage mode control architecture
with feed-forward and switches at a selectable frequency of
500kHz or 300kHz. Loop compensation is externally
adjustable to allow for an optimum balance between stability
and output dynamic performance. The internal synchronous
power switches are optimized for high efficiency and
excellent thermal performance.
The chip features two logic-level disable inputs that can be
used to inhibit pulses on the phase (LXx) pins in order to
maximize efficiency based on the load current. The
ISL70003SEH also supports DDR applications and contains a
buffer amplifier for generating the V_REF voltage.
High integration, best in class radiation performance and a
feature filled design make the ISL70003SEH an ideal choice
to power many of todays small form factor applications.
Applications
• FPGA, CPLD, DSP, CPU core and I/O supply voltages
• DDR memory supply voltages
• Low-voltage, high-density distributed power systems
Related Literature
• AN1897, ISL70003SEHEV1Z Evaluation Board
• AN1915, ISL70003SEH iSim:PE Model
• AN1913, Single Event Effects Testing of the ISL70003SEH,
3V to 13.2V, 6A Synchronous Buck Regulator
• AN1924, Total Dose Testing of the ISL70003SEH Radiation
Hardened Point Of Load Regulator
Features
• Acceptance tested to 50krad(Si) (LDR) wafer-by-wafer
• ±1% reference voltage over line, temperature and radiation
• Integrated MOSFETs 31mΩPFET/21mΩ NFET
- 95% peak efficiency
• Externally adjustable loop compensation
• Supports DDR applications (V_TT tracks V_DDQ/2)
- Buffer amplifier for generating V_REF voltage
- 3A current sinking capability
• Grounded lid eliminates charge build up
• IMON pin for output current monitoring
• Adjustable analog soft-start
• Diode emulation for increased efficiency at light loads
• 500kHz or 300kHz operating frequency synch wording
• Monotonic start-up into prebiased load
• Full military temperature range operation
- T_A = -55°C to +125°C
- T_J = -55°C to +150°C
• Radiation tolerance
- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)*
* Limit established by characterization.
• SEE hardness
- SEB and SEL LET_TH . . . . . . . . . . . . . . . . 86.4MeV•cm²/mg
- SET at LET 86.4MeV•cm²/mg . . . . . . . . . . . < ±3% ΔV_OUT
- SEFI LET_TH . . . . . . . . . . . . . . . . . . . . . . . . . 60MeV•cm²/mg
• Electrically screened to DLA SMD 5962-14203
100
95
90
85
80
75
70
65
60
55
50
0
3.3V
5V
2.5V
1
2
3
4
LOAD CURRENT (A)
9V
5
6
FIGURE 1. POWER DISTRIBUTION SOLUTION FOR RAD HARD LOW
POWER FPGA’s
FIGURE 2. EFFICIENCY vs LOAD, V_IN = 12V, f_SW = 300kHz
ALL OUTPUTS ACTIVE
May 12, 2016
1
FN8604.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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