ISL70003SEH Datasheet, PDF (17/32 Pages) Intersil Corporation – Acceptance tested to 50krad

ISL70003SEH
Functional Description
The ISL70003SEH is a monolithic synchronous buck regulator IC
with integrated power MOSFETs. The device utilizes voltage-mode
control with feed-forward and switches at a nominal frequency of
500kHz or 300kHz. It is fabricated on a 0.6μm BiCMOS junction
isolated process optimized for power management applications.
With this chip and a handful of external components, a complete
synchronous buck DC/DC converter can be readily implemented.
The converter accepts an input voltage ranging from 3V to 13.2V
and provides a tightly regulated output voltage ranging from 0.6V
to ~90% of the input voltage at output currents ranging from 0A
to 6A. Typical applications include Point Of Load (POL) regulation
for FPGAs, CPLDs, DSPs, DDR memory and microprocessors.
Power Blocks
PVIN1
LX1
PGND1
PVIN2
LX2
PGND2
POWER BLOCK 1
POWER BLOCK 6
OCPB and IMON
POWER BLOCK 2
POWER BLOCK 7
PVIN6
LX6
PGND6
PVIN7
LX7
PGND7
Initialization
The ISL70003SEH initializes based on the state of the EN input
and POR input. Successful initialization prompts a soft-start
interval and the regulator begins slowly ramping the output
voltage. Once the commanded output voltage is within the
proper window of operation, the power-good signal changes state
from low to high indicating proper regulator operation.
Enable
The EN pin accepts TTL/CMOS logic input as described in the
Electrical Specifications” table on page 9. When the voltage on
the EN pin exceeds its logic rising threshold, the controller
monitors the POR voltage before initiating the soft-start function
for the PWM regulator. When EN is pulled low, the device enters
shutdown mode and the supply current drops to a typical value of
1.5mA. All internal power devices are held in a high-impedance
state while in shutdown mode. Due to the internal 5V clamp, the
EN pin should be driven no higher than 5V or excessive leakage
current may be seen on the pin. In standalone applications the
EN pin may be tied to an input voltage >5V through a 50kΩ
resistor to minimize the current into the EN pin. The current
should not be allowed to exceed 160µA at any operating voltage.
PVIN3
LX3
PGND3
POWER BLOCK 3
POWER BLOCK 8
PVIN8
LX8
PGND8
PVIN4
LX4
PGND4
PVIN5
LX5
PGND5
POWER BLOCK 4
POWER BLOCK 9
POWER BLOCK 5
and OCPA
POWER BLOCK 10
PVIN9
LX9
PGND9
PVIN10
LX10
PGND10
Note: Shaded blocks indicate pilot current and current sensors.
FIGURE 36. POWER BLOCK DIAGRAM
The power output stage of the regulator consists of ten power
blocks that are paralleled to provide full 6A output current
capability at T_J = +125°C. The block diagram in Figure 36 shows
a top level view of the individual power blocks.
SEL1 and SEL2 pins allow users to disable power blocks in order
to reduce switching losses in light load applications. Depending
on the state of these pins the ISL70003SEH can operate with 2,
4, or 10 active power blocks and also be placed in a sleep mode.
Each power block has a power supply input pin, PVINx, a phase
output pin, LXx and a power supply ground pin, PGNDx. All PVINx
pins must be connected to a common power supply rail and all
PGNDx pins must be connected to a common ground. LXx pins
should be connected to the output inductor based on the
required load current and the state of the SEL1, SEL2 pins, but
must include the LX5 and LX6 pins. The unused LXx pins should
be left unconnected.
Scaled pilot devices associated with power blocks 5 and 6
provide current feedback for overcurrent detection and the IMON
current monitor feature. Power blocks 5 and 6 must be
connected to the output inductor at all times for proper
operation.
POR
LOGIC
ENABLE
COMPARATOR
+
- ^VR
V_IN > 5.0V
PVINx
R1
51kΩ
EN
FIGURE 37. ENABLE TO V_IN FOR >5.0 INPUT VOLTAGE
Power-On Reset
After the EN input requirements are met, the ISL70003SEH
remains in shutdown until the voltage at the POR pin rises above
its threshold. The POR circuitry prevents the controller from
attempting to soft-start before sufficient bias is present at the
PVINx pins.
As shown in Figure 38 on page 18, the POR circuit features a
comparator type input. The POR circuit allows the level of the
input voltage to precisely gate the turn-on/turn-off of the
regulator. An internal I_POR current sink with a typical value of
12µA is only active when the voltage on the POR pin is below the
enable threshold so it can pull the POR pin low. As V_IN rises, the
POR enable level is set by the resistor divider (R₁ and R₂) from
V_IN and the internal sink current source, I_POR.
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FN8604.5
May 12, 2016