ISL70003SEH Datasheet, PDF (23/32 Pages) Intersil Corporation – Acceptance tested to 50krad

ISL70003SEH
Each regulator has its own fault protections and must be
individually configured. All the sink current on the V_TT regulator is
provided by the VDDQ rail, the overcurrent protection on the
VDDQ rail will limit the amount of current that the V_TT rail will
sink.
When sinking current or at a no load condition, the inductor
valley current is negative, see Figure 28. During any time when
the inductor valley current is negative and the ISL70003 is
exposed to a heavy ion environment the abs max PVIN voltage
must be ≤13.7V, see Note 5 on page 9.
SEL1 and SEL2 may be tied together and used to place the V_TT
regulator in sleep mode, common to DDR applications. The
outputs will be tri-stated, however the buffer amplifier is still
active and the VREF voltage will be present even if the V_TT is in
sleep mode. When SEL1 and SEL2 are asserted low, the V_TT
regulator will ramp up the voltage. The ramp is controlled and
timing is based on soft-start capacitor value.
Refer to Figure 5 on page 8 for complete DDR power solution
typical application circuit schematic.
Derating Current Capability
Most space programs issue specific derating guidelines for parts,
but these guidelines take the pedigree of the part into account.
For instance, a device built to MIL-PRF-38535, such as the
ISL70003SEH, is already heavily derated from a current density
standpoint. However, a mil-temp or commercial IC that is
up-screened for use in space applications may need additional
current derating to ensure reliable operation because it was not
built to the same standards as the ISL70003SEH.
FIGURE 46. CURRENT vs TEMPERATURE
Figure 46 shows the maximum average output current of the
ISL70003SEH with respect to junction temperature. These plots
take into account the worst-case current share mismatch in the
power blocks and the current density requirement of
MIL-PRF-38535 (< 2 x 10⁵ A/cm²). The plot clearly shows that
the ISL70003SEH can handle 7A at +150°C from a worst-case
current density standpoint, but the part is rated to 3A. Therefore,
no further current derating of the ISL70003SEH is needed.
General Design Guide
This design guide is intended to provide a high-level explanation
of the steps necessary to design the power stage and feedback
compensation network of a single phase power converter. It is
assumed that the reader is familiar with many of the basic skills
and techniques in switch mode power supply design. In addition
to this guide, Intersil provides an evaluation board that includes
schematic, bills of materials and board layout.
Output Inductor Selection
The output inductor is selected to minimize the converter’s
response time to a load transient and meet steady state output
voltage ripple requirements. The inductor value determines the
converter’s inductor ripple current and the output voltage ripple
is a function of the inductor ripple current. The output voltage
ripple and the inductor ripple current are approximated by using
Equation 13:
I = ^V------^I---_f^N--_S-----^–-_W-----^V---_---^O----_L--^U------^T---  -^V---_V-^O---_I-^U-_N---^T--
V_OUT = I  ESR
(EQ. 13)
Increasing the value of inductance reduces the ripple current and
output voltage ripple. However, the large inductance values
reduce the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. The response time is the time required to slew the
inductor current from an initial current value to the transient
current level. During this interval the difference between the
inductor current and the transient current level must be
supplied by the output capacitor. Minimizing the response time
can minimize the output capacitance required.
The response time to a transient is different for the application of
load and the removal of load. Equation 14, gives the approximate
response time interval for application and removal of a transient
load.
t_RISE =
L x I_TRAN
V_IN - V_OUT
t_FALL =
L x I_TRAN
V_OUT
(EQ. 14)
Where I_TRAN is the transient load current step, t_RISE is the
response time to the application of load, and t_FALL is the
response time to the removal of load. The worst case response
time can be either at the application or removal of load. Be sure
to check both Equations 13 and 14 at the minimum and
maximum output levels for the worst case response time.
Output Capacitor Selection
An output capacitor is required to filter the inductor current and
supply the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current. The
load transient requirements are a function of the slew rate (di/dt)
and the magnitude of the transient load current. These
requirements are generally met with a mix of capacitors and
careful layout.
High-frequency capacitors initially supply the transient and slow
the current load rate seen by the bulk capacitors. The bulk filter
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FN8604.5
May 12, 2016