ISL70003SEH Datasheet, PDF (20/32 Pages) Intersil Corporation – Acceptance tested to 50krad

ISL70003SEH
Switching Frequency Selection
There are a number of variables to consider when choosing the
switching frequency. A high switching frequency increases the
switching losses but may lead to a decrease in output filter size.
A lower switching frequency may increase efficiency but may
lead to more output voltage ripple and increased output filter
size.
On the ISL70003SEH the switching frequency is determined by
the state of the TTL/CMOS compatible FSEL pin. A logic low will
set the regulator to operate with a 500kHz switching frequency,
while a logic high sets a 300kHz switching frequency.
Synchronization
The ISL70003SEH can be synchronized to an external clock with
a frequency range of 500kHz ±15% or 300kHz ±15%, depending
on the state of the FSEL pin.
The SYNC pin accepts the external clock signal and the regulator
will be synchronized in phase with the external clock. During
start-up the regulator will use its internal oscillator to regulate
the output voltage. Once soft-start is complete and PGOOD is
released, the regulator will synchronize to the external clock
signal. This feature allows the ISL70003SEH regulator to be the
power source to the external components that will be providing
the external clock without the requirement that a signal must be
present at the SYNC pin before start-up.
Output Voltage Selection
ERROR
AMPLIFIER
-
+
V_REF
LXx ^LO
V_OUT
C_O
R₁
FB
NI
R₄
REF
C_REF
FIGURE 41. OUTPUT VOLTAGE SELECTION
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage
relative to the reference voltage. The reference voltage and the
non-inverting input to the error amplifier are not internally
connected, therefore, for standalone applications the REF pin
must be tied to the NI pin (see Figure 41). The REF pin should be
bypassed to AGND with a 220nF ceramic capacitor to mitigate
SEE. It should be noted that no current (sourcing or sinking) is
available from the REF pin.
The output voltage programming resistor, R₄, will depend on the
value chosen for the feedback resistor R₁ and the desired output
voltage of the regulator. The value for the feedback resistor is
typically between 5kΩ and 25kΩ.
R₄ = -V---R-_O-----^1U-----_T-^-----_–--⁰----0^.---⁶--.--6-^V----V---
(EQ. 6)
If the output voltage desired is 0.6V, then R₄ is left unpopulated.
Setting the Overcurrent Protection Level
The ISL70003SEH features dual redundancy in the overcurrent
detection circuitry, which helps avoid false overcurrent triggering
due to single event effects. Two external resistors from pins
OCSETA and OCSETB to AGND set the level of the over current
protection (OCP) trip point. The OCP circuit senses the peak
current across a pilot device not the average current so it is
important to determine the overcurrent trip point (I_OCP) greater
than the maximum output continuous current (I_MAX) plus half
the maximum inductor ripple current (ΔI).
Use Equation 7 to determine the inductor ripple current:
I = ^V-----^I-_f-^N-_S----–_W----^V---_--^O--_L--^U----^T--  D
(EQ. 7)
Where f_SW is the switching frequency, L is the output inductor
value and D is duty cycle. Once an I_OCP value is chosen that
satisfies Equation 8:
I_OCP  I_MAX + ^--₂---^I
(EQ. 8)
Equation 9 may be used to determine the value of R_OCSETA and
R_OCSETB with all 10 power blocks active.
R_{OCSETA B} = ³--_I--_O⁶---⁰-_C--²--_P--⁴--
(EQ. 9)
The minimum value for R_OCSET(A,B) is 2.94kΩ which is
equivalent to a 12.25A I_OCP level.
Disabling the Power Blocks
The ISL70003SEH offers two TTL/CMOS compatible power block
select pins, SEL1 and SEL2, which form a two-bit logic input that
are used to turn off the internal power blocks. Depending on the
state of the SEL1 and SEL2 pins, the ISL70003SEH can operate
with 2, 4 or 10 power blocks on or have all the outputs in a
tr-state mode. This allows the designer to reduce switching
losses in low current applications, where all power blocks are not
needed to supply the load current. Table 1 on page 20 compares
the logic state of SEL1 and SEL2 with the current capability of the
regulator and the number of active LXx pins.
SEL2
STATE
0
TABLE 1. LOGIC STATE COMPARISON
SEL1
STATE
ACTIVE LXx PINS
LOAD CAPABILITY
(T_J = +125°C)
0
All
6A
0
1
5, 6, 7, 8
2.4A
1
0
5, 6
1.2A
1
1
None
N/A
With both SEL pins in a logic high state, the ISL70003SEH is in a
low power sleep mode where all outputs are tri-stated. Once the
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FN8604.5
May 12, 2016