ISL6265C_10 Datasheet, PDF (25/27 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

ISL6265C
less noise traces with high dV/dt and di/dt, such as gate
signals and phase node signals.
Signal Ground and Power Ground
The bottom of the ISL6265C QFN package is the signal
ground (GND) terminal for analog and logic signals of the
IC. Connect the GND pad of the ISL6265C to the island
of ground plane under the top layer using several vias,
for a robust thermal and electrical conduction path.
Connect the input capacitors, the output capacitors, and
the source of the lower MOSFETs to the power ground
plane.
Routing and Connection Details
Specific pins (and the trace routing from them), require
extra attention during the layout process. The following
sub-sections outline concerns by pin name.
PGND PINS
This is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path.
VIN PIN
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low- resistance and
low-inductance path.
VCC PIN
For best performance, place the decoupling capacitor
very close to the VCC and GND pins.
PVCC PIN
For best performance, place the decoupling capacitor
very close to the PVCC and respective PGND pins,
preferably on the same side of the PCB as the ISL6265C
IC.
ENABLE AND PGOOD PINS
These are logic signals that are referenced to the GND
pin. Treat as a typical logic signal.
FB PINS
The input impedance of the FB pin is high, so place the
voltage programming and loop compensation
components close to the COMP, FB, and GND pins
keeping the high impedance trace short.
FSET_NB PIN
This pin requires a quiet environment. The resistor R_FSET
should be placed directly adjacent to this pin. Keep fast
moving nodes away from this pin.
LGATE ROUTING
The LGATE trace has a signal going through it that is both
high dV/dt and di/dt, with high peak charging and
discharging current. Route this trace in parallel with the
trace from the PGND pin. These two traces should be
short, wide, and away from other traces. There should be
no other weak signal traces in proximity with these
traces on any layer.
BOOT AND PHASE ROUTING
The signals going through these traces are both high
dv/dt and high di/dt, with high peak charging and
discharging current. Route the UGATE and PHASE pins in
parallel with short and wide traces. There should be no
other weak signal traces in proximity with these traces
on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing.
It is best to limit the size of the PHASE node copper in
strict accordance with the current and thermal
management of the application. An MLCC should be
connected directly across the drain of the upper MOSFET
and the source of the lower MOSFET to suppress the
turn-off voltage.
25
FN6976.1
July 28, 2010