ISL6265C_10 Datasheet, PDF (18/27 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

ISL6265C
TABLE 4. SVI SEND BYTE ADDRESS DESCRIPTION
BITS
DESCRIPTION
2 VDD1, if set then the following data byte contains the
VID for VDD1
1 VDD0, if set then the following data byte contains the
VID for VID0
0 VDDNB, if set then the following data byte contains the
VID for VIDNB
TABLE 5. SERIAL VID 8-BIT DATA FIELD ENCODING
BITS
DESCRIPTION
7 PSI_L:
=0 means the processor is at an optimal load for the
regulator(s) to enter power-savings mode
=1 means the processor is not at an optimal load for
the regulator(s) to enter power-saving mode
6:0 SVID[6:0] as defined in Table 3.
Operation
After the start-up sequence, the ISL6265C begins
regulating the core and Northbridge output voltages to
the pre-PWROK metal VID programmed. The controller
monitors SVI commands to determine when to enter
power-savings mode, implement dynamic VID changes,
and shutdown individual outputs.
The ISL6265C controls the no-load output voltage of core
and Northbridge output to an accuracy of ±0.5% over-
the-range of 0.75V to 1.5V. A fully differential amplifier
implements core voltage sensing for precise voltage
control at the microprocessor die.
Switching Frequency
The R³ modulator scheme is a variable frequency PWM
architecture. The switching frequency increases during
the application of a load to improve transient
performance. It also varies slightly due to changes in
input and output voltage and output current. This
variation is normally less than 10% in continuous
conduction mode.
CORE FREQUENCY SELECTION
A resistor connected between the VW and COMP pins of
the Core segment of the ISL6265C adjusts the switching
window and therefore adjusts the switching frequency.
The R_FSET resistor that sets up the switching frequency of
the converter operating in CCM can be determined using
Equation 3, where R_FSET is in kΩ and the switching period
is in ms. Designs for 300kHz switching frequency would
result in a R_FSET value of 6.81kΩ.
R_FSET(kΩ) = (Period(μs) – 0.4) × 2.33
(EQ. 3)
In discontinuous conduction mode (DCM) the ISL6265C
runs in period stretching mode.
NORTHBRIDGE FREQUENCY SELECTION
The Northbridge switching frequency to programmed by
a resistor connected from the FSET_NB pin to the GND
pin. The approximate PWM switching frequency is written
as shown in Equation 4:
F_SW = _K------_â‹---_R-----_F---¹_S----_E----_T----_N----_B--
(EQ. 4)
Estimating the value of R_{FSET_NB} is written as shown in
Equation 5:
R_FSET = -_K-----_â‹---_F1----_S----_W---
(EQ. 5)
Where F_SW is the PWM switching frequency, R_{FSET_NB} is
the programming resistor and K = 1.5 x 10^-10.
It is recommended that whenever the control loop
compensation network is modified, the switching
frequency should be checked and adjusted by changing
R_{FSET_NB} if necessary.
Current Sense
Core and Northbridge regulators feature two different
types of current sense circuits.
CORE CONTINUOUS CURRENT SENSE
The ISL6265C provides for load current to be measured
using either resistors in series with the individual output
inductors or using the intrinsic series resistance of the
inductors as shown in the applications circuits in
Figures 2 and 3. The load current in a particular output is
sampled continuously every switching cycle. During this
time, the current-sense amplifier uses the current sense
inputs to reproduce a signal proportional to the inductor
current. This sensed current is a scaled version of the
inductor current.
MOSFET
DRIVER
UGATE
LGATE
V_IN
IL
L
DCR
INDUCTOR
V_L(s)
V_C(s)
R₁
C₁
ISL6265C INTERNAL CIRCUIT
R₂
V_OUT
C_OUT
CURRENT
SENSE
ISP
ISN
R_{NTC OPTIONAL}
NTC
R_{3 NETWORK}
FIGURE 9. DCR SENSING COMPONENTS
18
FN6976.1
July 28, 2010