ISL6265C_10 Datasheet, PDF (13/27 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

ISL6265C
ISL6265C Gate Driver Timing Diagram
PWM
UGATE
t_PDHU
t_RU
t_FU
1V
LGATE
1V
t_FL
t_RL
t_PDHL
Theory of Operation
The ISL6265C is a flexible multi-output controller
supporting Northbridge and single or dual power planes
required by Class M AMD Mobile CPUs. In single plane
applications, both core voltage regulators operate
single-phase. In uniplane core applications, the core
voltage regulators are configured to operate as a
two-phase regulator. All three regulator outputs include
integrated gate drivers for reduced system cost and
small board area. The regulators provide optimum
steady-state and transient performance for
microprocessor applications. System efficiency is
enhanced by idling a phase in uniplane configurations at
low-current and implementing automatic DCM-mode
operation when PSI_L is asserted to logic low.
The heart of the ISL6265C is the R³ Technology™,
Intersil's Robust Ripple Regulator modulator. The R³
modulator combines the best features of fixed frequency
PWM and hysteretic PWM while eliminating many of their
shortcomings. The ISL6265C modulator internally
synthesizes an analog of the inductor ripple current and
uses hysteretic comparators on those signals to establish
PWM pulse widths. Operating on these large-amplitude,
noise-free synthesized signals allows the ISL6265C to
achieve lower output ripple and lower phase jitter than
either conventional hysteretic or fixed frequency PWM
controllers. Unlike conventional hysteretic converters,
the ISL6265C has an error amplifier that allows the
controller to maintain a 0.5% voltage regulation accuracy
throughout the VID range from 0.75V to 1.55V. Voltage
regulation accuracy is slightly wider, ±5mV, over the VID
range from 0.7375V to 0.5V.
The hysteresis window voltage is relative to the error
amplifier output such that load current transients result
in increased switching frequency, which gives the R³
regulator a faster response than conventional fixed
frequency PWM controllers. In uniplane configurations,
transient load current is inherently shared between
active phases due to the use of a common hysteretic
window voltage. Individual average phase currents are
monitored and controlled to equally share current among
the active phases.
Modulator
The ISL6265C modulator features Intersil’s R³
technology, a hybrid of fixed frequency PWM control and
variable frequency hysteretic control (see Figure 5).
Intersil’s R³ technology can simultaneously affect the
PWM switching frequency and PWM duty cycle in
response to input voltage and output load transients. The
R³ modulator synthesizes an AC signal V_R, which is an
analog representation of the output inductor ripple
current. The duty-cycle of V_R is the result of charge and
discharge current through a ripple capacitor C_R. The
current through C_R is provided by a transconductance
amplifier g_m that measures the VIN and VO voltages. The
positive slope of V_R can be written as determined by
Equation 1:
V_RPOS = (g_m) ⋅ (V_IN – V_OUT)
(EQ. 1)
The negative slope of V_R can be written as determined by
Equation 2:
V_RNEG = g_m ⋅ V_OUT
(EQ. 2)
Where g_m is the gain of the transconductance amplifier.
A window voltage V_W is referenced with respect to the
error amplifier output voltage V_COMP, creating an
envelope into which the ripple voltage V_R is compared.
The amplitude of V_W is set by a resistor connected across
the FSET and GND pins. The V_R, V_COMP, and V_W signals
feed into a window comparator in which V_COMP is the
lower threshold voltage and V_W is the higher threshold
voltage. Figure 6 shows PWM pulses being generated as
V_R traverses the V_W and V_COMP thresholds. The PWM
switching frequency is proportional to the slew rates of
the positive and negative slopes of V_R; it is inversely
proportional to the voltage between V_W and V_COMP.
13
FN6976.1
July 28, 2010