ISL6265C_10 Datasheet, PDF (24/27 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

ISL6265C
preferred high-side MOSFET emphasizes low gate charge
so that the device spends the least amount of time
dissipating power in the linear region. The preferred
low-side MOSFET emphasizes low r _DS(ON) when fully
saturated to minimize conduction loss.
For the low-side (LS) MOSFET, the power loss can be
assumed to be conductive only and is written as
Equation 24:
P_{CON_LS} ≈ I_LOAD2 ⋅ r_{DS(ON)_LS} • (1 – D)
(EQ. 24)
For the high-side (HS) MOSFET, the its conduction loss is
written as Equation 25:
P_{CON_HS} = I_LOAD2 • r_{DS(ON)_HS} • D
(EQ. 25)
For the high-side MOSFET, the switching loss is written as
Equation 26:
P_{SW_HS}
=
-^V----^I--^N----^•---^I--^V----^A----^L---^L---^E----^Y-----^•--^t--^O-----^N----^•---^f--^S----^W---
2
+
-^V----^I--^N----^•---^I--^P----^E----^A----^K----^•---^t--^O----^F----^F----^•---^f-^S----^W----
2
(EQ. 26)
Where:
- I_VALLEY is the difference of the DC component of
the inductor current minus 1/2 of the inductor
ripple current
- I_PEAK is the sum of the DC component of the
inductor current plus 1/2 of the inductor ripple
current
- t_ON is the time required to drive the device into
saturation
- t_OFF is the time required to drive the device into
cut-off
Selecting The Bootstrap Capacitor
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor
across the BOOT and PHASE pins completes the
bootstrap circuit. The bootstrap function is also designed
to prevent the bootstrap capacitor from overcharging due
to the large negative swing at the PHASE node. This
reduces voltage stress on the BOOT and PHASE pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 4V and its capacitance value is
selected per Equation 27:
C_BOO
T
≥
---------^Q-----^g---------
ΔV_BOOT
(EQ. 27)
Where:
- Q_g is the total gate charge required to turn on the
high-side MOSFET
- ΔV_BOOT, is the maximum allowed voltage decay
across the boot capacitor each time the high-side
MOSFET is switched on
As an example, suppose the high-side MOSFET has a
total gate charge Q_g, of 25nC at V_GS = 5V, and a ΔV_BOOT
of 200mV. The calculated bootstrap capacitance is
0.125µF; for a comfortable margin, select a capacitor
that is double the calculated capacitance. In this
example, 0.22µF will suffice. Use a low
temperature-coefficient ceramic capacitor.
PCB Layout Considerations
Power and Signal Layers Placement on the
PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with the weak
analog or logic signal layers on the opposite side of the
board. The ground-plane layer should be adjacent to the
signal layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the FSET components.
The island should be connected to the rest of the ground
plane layer at one point.
Component Placement
There are two sets of critical components in a DC/DC
converter; the power components and the small signal
components. The power components are the most critical
because they switch large amount of energy. The small
signal components connect to sensitive nodes or supply
critical bypassing current and signal coupling.
The power components should be placed first and these
include MOSFETs, input and output capacitors, and the
inductor. It is important to have a symmetrical layout for
each power train, preferably with the controller located
equidistant from each power train. Symmetrical layout
allows heat to be dissipated equally across all power
trains. Keeping the distance between the power train and
the control IC short helps keep the gate drive traces
short. These drive signals include the LGATE, UGATE,
PGND, PHASE and BOOT.
VIAS TO
GROUND
PLANE
INDUCTOR
HIGH-SIDE
MOSFETS
GND
VOUT
PHASE
NODE
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
VIN
CAPACITORS
FIGURE 13. TYPICAL POWER COMPONENT PLACEMENT
When placing MOSFETs, try to keep the source of the
upper MOSFETs and the drain of the lower MOSFETs as
close as thermally possible (see Figure 13). Input
high-frequency capacitors should be placed close to the
drain of the upper MOSFETs and the source of the lower
MOSFETs. Place the output inductor and output
capacitors between the MOSFETs and the load.
High-frequency output decoupling capacitors (ceramic)
should be placed as close as possible to the decoupling
target (microprocessor), making use of the shortest
connection paths to any internal planes. Place the
components in such a way that the area under the IC has
24
FN6976.1
July 28, 2010