ISL6265C_10 Datasheet, PDF (20/27 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

ISL6265C
Where V_OFS is the user defined output voltage offset.
Typically, V_OFS is determined by taking half the total
output voltage droop. The resulting value centers the
overall output voltage waveform around the programmed
SVID level. For example, R_FB of 1kΩ and a total output
droop of 24mV would result in an offset voltage of 12mV
and a R_OFS of 100kΩ.
Internal Driver Operation
The ISL6265C features three internal gate-drivers to
support the Core and Northbridge regulators and to
reduce solution size. The drivers include a diode
emulation mode, which helps to improve light-load
efficiency.
MOSFET Gate-Drive Outputs
The ISL6265C has internal gate-drivers for the high-side
and low-side N-Channel MOSFETs. The low-side gate-
drivers are optimized for low duty-cycle applications
where the low-side MOSFET conduction losses are
dominant, requiring a low r_DS(ON) MOSFET. The LGATE
pull-down resistance is low in order to strongly clamp the
gate of the MOSFET below the V_GS(th) at turn-off. The
current transient through the gate at turn-off can be
considerable because the gate charge of a low r_DS(ON)
MOSFET can be large. Adaptive shoot-through protection
prevents a gate-driver output from turning on until the
opposite gate-driver output has fallen below
approximately 1V.
The high-side gate-driver output voltage is measured
across the UGATE and PHASE pins while the low-side
gate-driver output voltage is measured across the LGATE
and PGND pins. The power for the LGATE gate driver is
sourced directly from the PVCC pin. The power for the
UGATE gate-driver is sourced from a “boot” capacitor
connected across the BOOT and PHASE pins. The boot
capacitor is charged from a 5V bias supply through a
“boot diode” each time the low-side MOSFET turns on,
pulling the PHASE pin low. The ISL6265C has an
integrated boot diode connected from the PVCC pin to
the BOOT pin.
Diode Emulation
The ISL6265C implements forced
continuous-conduction-mode (CCM) at heavy load and
diode-emulation-mode (DE) at light load, to optimize
efficiency in the entire load range. The transition is
automatically achieved by detecting the inductor current
when PSI_L is low. If PSI_L is high, the controller
disables DE and forces CCM on both Core and NB
regulators.
Positive-going inductor current flows either from the
source of the high-side MOSFET, or into the drain of the
low-side MOSFET. Negative-going inductor current flows
into the drain of the low-side MOSFET. When the low-side
MOSFET conducts positive inductor current, the phase
voltage is negative with respect to the GND and PGND
pins. Conversely, when the low-side MOSFET conducts
negative inductor current, the phase voltage is positive
with respect to the GND and PGND pins. The ISL6265C
monitors the phase voltage when the low-side MOSFET is
conducting inductor current to determine the direction of
the inductor current.
When the output load current is less than half the
inductor ripple current, the inductor current goes
negative. Sinking the negative inductor through the low-
side MOSFET lowers efficiency by preventing DCM period
stretching and allowing unnecessary conduction losses.
In DE, the ISL6265C Core regulators automatically enter
DCM after the PHASE pin has detected positive voltage
and LGATE was allowed to go high. The NB regulator
enters DCM after the PHASE pin has detected positive
voltage and LGATE was allowed to go high for eight
consecutive PWM switching cycles. The ISL6265C turns
off the low-side MOSFET once the phase voltage turns
positive, indicating negative inductor current. The
ISL6265C returns to CCM on the following cycle after the
PHASE pin detects negative voltage, indicating that the
body diode of the low-side MOSFET is conducting positive
inductor current.
Efficiency can be further improved with a reduction of
unnecessary switching losses by reducing the PWM
frequency. It is characteristic of the R³ architecture for
the PWM frequency to decrease while in diode emulation.
The extent of the frequency reduction is proportional to
the reduction of load current. Upon entering DCM, the
PWM frequency makes an initial step-reduction because
of a 33% step-increase of the window voltage V_W.
Power-Savings Mode
The ISL6265C has two operating modes to optimize
efficiency based on the state of the PSI_L input from the
AMD SVI control signal. When this input is low, the
controller expects to deliver low power and enters a
power-savings mode to improve efficiency in this low
power state. The controller’s operational modes are
designed to work in conjunction with the AMD SVI control
signal to maintain the optimal system configuration for
all conditions.
Northbridge And Dual Plane Core
While PSI_L is high, the controller operates all three
regulators in forced CCM. If PSI_L is asserted low by the
SVI interface, the ISL6265C initiates DE in all three
regulators. This transition allows the controller to achieve
the highest possible efficiency over the entire load range
for each output. A smooth transition is facilitated by the
R³ technology^™, which correctly maintains the internally
synthesized ripple current throughout mode transitions
of each regulator.
Uniplane Core
In uniplane mode, the ISL6265C Core regulator is in
2-phase multiphase mode. The controller operates with
both phases fully active, responding rapidly to transients
and delivering the maximum power to the load. When
the processor asserts PSI_L low under reduced load
levels, the ISL6265C sheds one phase to eliminate
switching losses associated with the idle channel. Even
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FN6976.1
July 28, 2010