ISL6265C_10 Datasheet, PDF (15/27 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

ISL6265C
TABLE 1. PRE-PWROK METAL VID CODES
SVC
SVD
OUTPUT VOLTAGE (V)
0
0
1.1
0
1
1.0
1
0
0.9
1
1
0.8
If the EN input falls below the enable falling threshold,
the ISL6265C tri-states all outputs. PGOOD is pulled low
with the loss of EN. The Core and Northbridge planes will
decay based on output capacitance and load leakage
resistance. If bias to VCC falls below the POR level, the
ISL6265C responds in the same manner previously
described. Once VCC and EN rise above their respective
rising thresholds, the internal DAC circuitry re-acquires a
pre-PWROK metal VID code and the controller
soft-starts.
VFIX MODE
In VFIX Mode, the SVC and SVD levels fixed external to
the controller through jumpers to either GND or VDDIO.
These inputs are not expected to change. In VFIX mode,
the IC decodes the SVC and SVD states per Table 2.
SVC
0
0
1
1
TABLE 2. VFIXEN VID CODES
SVD
OUTPUT VOLTAGE (V)
0
1.4
1
1.2
0
1.0
1
0.8
Once enabled, the ISL6265C begins to soft-start both
Core and Northbridge planes to the programmed VFIX
level. The internal soft-start circuitry slowly ramps the
reference up to the target value. The same fixed internal
rate of approximately 2mV/µs results in a controlled
ramp of the power planes. Once soft-start has ended and
all output planes are within regulation limits, the PGOOD
pin transitions high.
VCC
1
2
3
456
7
8
9 10
11
12
SVC
SVD
ENABLE
PWROK
DD AND VDDNB
METAL_VID
V_SVI
METAL_VID
V_SVI
VDDPWRGD
(PGOOD)
FIXEN
Interval 1 to 2: ISL6265C waits to POR.
Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code.
Interval 3 to 4: EN locks core output configuration and pre-Metal VID code. All outputs soft-start to this level.
Interval 4 to 5: PGOOD signal goes HIGH indicating proper operation.
Interval 5 to 6: CPU detects VDDPWRGD high and drives PWROK high to allow ISL6265C to prepare for SVI code.
Interval 6 to 7: SVC and SVD data lines communicate change in VID code.
Interval 7 to 8: ISL6265C responds to VID-ON-THE-FLY code change.
Interval 8 to 9: PWROK is driven low and ISL6265C returns all outputs to pre-PWROK Metal VID level.
Interval 9 to 10: PWROK driven high once again by CPU and ISL6265C prepares for SVI code.
Interval 10 to 11: SVC and SVD data lines communicate new VID code.
Interval 11 to 12: ISL6265C drives outputs to new VID code level.
Post 12 : Enable falls and all internal drivers are tri-stated and PGOOD is driven low.
FIGURE 7. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID STARTUP
15
FN6976.1
July 28, 2010