ISL6265C_10 Datasheet, PDF (17/27 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

ISL6265C
TABLE 3. SERIAL VID CODES (Continued)
SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V)
000_1100b
1.4000
010_1100b
1.0000
100_1100b
0.6000
000_1101b
1.3875
010_1101b
0.9875
100_1101b
0.5875
000_1110b
1.3750
010_1110b
0.9750
100_1110b
0.5750
000_1111b
1.3625
010_1111b
0.9625
100_1111b
0.5625
001_0000b
1.3500
011_0000b
0.9500
101_0000b
0.5500
001_0001b
1.3375
011_0001b
0.9375
101_0001b
0.5375
001_0010b
1.3250
011_0010b
0.9250
101_0010b
0.5250
001_0011b
1.3125
011_0011b
0.9125
101_0011b
0.5125
001_0100b
1.3000
011_0100b
0.9000
101_0100b
0.5000
001_0101b
1.2875
011_0101b
0.8875
101_0101b
0.4875*
001_0110b
1.2750
011_0110b
0.8750
101_0110b
0.4750*
001_0111b
1.2625
011_0111b
0.8625
101_0111b
0.4625*
001_1000b
1.2500
011_1000b
0.8500
101_1000b
0.4500*
001_1001b
1.2375
011_1001b
0.8375
101_1001b
0.4375*
001_1010b
1.2250
011_1010b
0.8250
101_1010b
0.4250*
001_1011b
1.2125
011_1011b
0.8125
101_1011b
0.4125*
001_1100b
1.2000
011_1100b
0.8000
101_1100b
0.4000*
001_1101b
1.1875
011_1101b
0.7875
101_1101b
0.3875*
001_1110b
1.1750
011_1110b
0.7750
101_1110b
0.3750*
001_1111b
1.1625
011_1111b
0.7625
101_1111b
0.3625*
NOTE: *Indicates a VID not required for AMD Family 10h processors.
SVID[6:0]
110_1100b
110_1101b
110_1110b
110_1111b
111_0000b
111_0001b
111_0010b
111_0011b
111_0100b
111_0101b
111_0110b
111_0111b
111_1000b
111_1001b
111_1010b
111_1011b
111_1100b
111_1101b
111_1110b
111_1111b
VOLTAGE (V)
0.2000*
0.1875*
0.1750*
0.1625*
0.1500*
0.1375*
0.1250*
0.1125*
0.1000*
0.0875*
0.0750*
0.0625*
0.0500*
0.0375*
0.0250*
0.0125*
OFF
OFF
OFF
OFF
SVC
SVD
6 5 4 32 10
SLAVE ADDRESS PHASE
(See Table 3)
SVID
7 654 3 210
DATA PHASE
FIGURE 8. SEND BYTE EXAMPLE
SVI Bus Protocol
The AMD processor bus protocol is compliant with SMBus
send byte protocol for VID transactions (see Figure 8).
During a send byte transaction, the processor sends the
start sequence followed by the slave address of the VR
for which the VID command applies. The address byte
must be configured according to Table 4. The processor
then sends the write bit. After the write bit, if the
ISL6265C receives a valid address byte, it sends the
acknowledge bit. The processor then sends the PSI-L bit
and VID bits during the data phase. The Serial VID 8-bit
data field encoding is outlined in Table 5. If ISL6265C
receives a valid 8-bit code during the data phase, it
sends the acknowledge bit. Finally, the processor sends
the stop sequence. After the ISL6265C has detected the
stop, it can then proceed with the VID-on-the-fly
transition.
TABLE 4. SVI SEND BYTE ADDRESS DESCRIPTION
BITS
DESCRIPTION
6:4 Always 110b
3 Reserved by AMD for future use
17
FN6976.1
July 28, 2010