ISL6265C_10 Datasheet, PDF (19/27 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

ISL6265C
Inductor windings have a characteristic distributed
resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 9. The inductor
current, I_L, flowing through the inductor, passes through
the DCR. Equation 6 shows the s-domain equivalent
voltage, V_L, across the inductor.
V_L(s) = I_L ⋅ (s ⋅ L + DCR)
(EQ. 6)
A simple R-C network across the inductor (R₁, R₂ and C)
extracts the DCR voltage, as shown in Equation 7. The
voltage across the sense capacitor, V_C, can be shown to
be proportional to the output current I_L, shown in
Equation 7.
⎛
⎝
--^s-----^â‹---^L---
DCR
+
1_⎠⎞
V_C(s)
=
----------------------------------------------------------
⎛
⎜
⎝
s
⋅
(_---R_-----1----⋅_---R_-----2---)
R₁ + R₂
⋅
C₁
+
⎞
1⎟
⎠
⋅
K
⋅
DCR
⋅
I_L
(EQ. 7)
Where:
K
=
-------^R-----²--------
R₂ + R₁
(EQ. 8)
Sensing the time varying inductor current accurately
requires that the parallel R-C network time constant
match the inductor L/DCR time constant. If the R-C
network components are selected, such that the R-C
time constant matches the inductor L/DCR time constant
(see Equation 9), then V_C is equal to the voltage drop
across the DCR multiplied by the ratio of the resistor
divider, K.
------^L-------
DCR
=
-^R-----¹----^â‹---^R-----²--
R₁ + R₂
⋅
C₁
(EQ. 9)
The inductor current sense information is used for
current balance in dual plane applications, overcurrent
detection in core outputs and output voltage droop
depending on controller configuration.
CORE DCR TEMPERATURE COMPENSATION
It may also be necessary to compensate for changes in
inductor DCR due to temperature. DCR shifts due to
temperature cause time constant mismatch, skewing
inductor current accuracy. Potential problems include
output voltage droop and OC trip point, both shifting
significantly from expected levels. The addition of a
negative temperature coefficient (NTC) resistor to the
R-C network compensates for the rise in DCR due to
temperature. Typical NTC values are in the 10kΩ range. A
second resistor, R₃, in series with the NTC allows for
more accurate time-constant and resistor-ratio matching
as the pair of resistors are placed in parallel with R₂
(Figure 9). The NTC resistor must be placed next to the
inductor for good heat transfer, while R₁, R₂, R₃, and C₁
are placed close to the controller for interference
immunity.
CORE DCR COMPONENT SELECTION FOR DROOP
By adjusting the ratio between inductor DCR drop and
the voltage measured across the sense capacitor, the
load line can be set to any level, giving the converter the
correct amount of droop at all load currents.
Equation 10 shows the relation between droop voltage,
maximum output current (I_MAX), OC trip level and
current sense capacitor voltage at the OC current level,
V_C(OC).
V_DROOP
=
I_{--M-----A----X--}
I_OC
⋅
5
⋅
V_C,
OC
(EQ. 10)
AMD specifications do not require droop and provide no
load line guidelines. Tight static output voltage tolerance
limits push acceptable level of droop below a useful level
for Griffin applications. Care must be taken in
applications which implement droop to balance time
constant mismatch, sense capacitor resistor ratio, OC trip
and droop equations. Temperature shifts related to DCR
must also be addressed, as outlined in the previous
section.
NORTHBRIDGE CURRENT SENSE
During the off-time following a PHASE transition low, the
Northbridge controller samples the voltage across the
lower MOSFET r_DS(ON). A ground-referenced amplifier is
connected to the PHASE node through a resistor,
R_{OCSET_NB}. The voltage across R_{OCSET_NB} is equal to the
voltage drop across the r_DS(ON) of the lower MOSFET
while it is conducting. The resulting current into the
OCSET_NB pin is proportional to the inductor current.
The sensed inductor current is used for overcurrent
protection and described in the “Fault Monitoring and
Protection” on page 21. The Northbridge controller does
not support output voltage droop.
Selecting RBIAS For Core Outputs
To properly bias the ISL6265C, a reference current is
established by placing a 117kΩ, 1% tolerance resistor
from the RBIAS pin to ground. This will provide a highly
accurate, 10µA current source from which OC reference
current is derived.
Care must be taken in layout to place the resistor very
close to the RBIAS pin. A good quality signal ground
should be connected to the opposite end of the R_BIAS
resistor. Do not connect any other components to this pin
as this would negatively impact performance.
Capacitance on this pin could create instabilities and is to
be avoided.
A resistor divider off this pin is used to set the Core side
OC trip level. Additional direction on how to size is
provided in “Fault Monitoring and Protection” on page 21
on how to size the resistor divider.
Offset Resistor Selection
If the OFS pin is connected to ground through a resistor,
the ISL6265C operates in SVI mode with droop active.
The resistor between the OFS pin and ground sets the
positive Core voltage offset per Equation 11.
R_OFS
=
1_----._--2_---V_------⋅_---R_----F----B--
V_OFS
(EQ. 11)
19
FN6976.1
July 28, 2010