ISL6265C_10 Datasheet, PDF (23/27 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

ISL6265C
ESR and of the voltage change stemming from charge
moved in and out of the capacitor. These two voltages
are written as shown in Equation 20:
ΔV_ESR = I_PP • ESR
(EQ. 20)
and Equation 21:
ΔV_C
=
-----------^I--^P----^P------------
8 • C_O • f_SW
(EQ. 21)
If the output of the converter has to support a load with
high pulsating current, several capacitors will need to be
paralleled to reduce the total ESR until the required V_P-P
is achieved. The inductance of the capacitor can cause a
brief voltage dip if the load transient has an extremely
high slew rate. Capacitor ESL can significantly impact
output voltage ripple. Low inductance capacitors should
be considered. A capacitor dissipates heat as a function
of RMS current and frequency. Be sure that I_P-P is
shared by a sufficient quantity of paralleled capacitors
so that they operate below the maximum rated RMS
current at F_SW. Take into account that the rated value of
a capacitor can degrade as much as 50% as the DC
voltage across it increases.
Selection of the Input Capacitor
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capability must be sufficient
to handle the AC component of the current drawn by the
upper MOSFETs, which is related to duty cycle and the
number of active phases.
The important parameters for the bulk input capacitance
are the voltage rating and the RMS current rating. For
reliable operation, select bulk capacitors with voltage and
current ratings above the maximum input voltage and
capable of supplying the RMS current required by the
switching circuit. Their voltage rating should be at least
1.25x greater than the maximum input voltage, while a
voltage rating of 1.5x is a preferred rating. Figure 11 is a
graph of the input RMS ripple current, normalized
relative to output load current, as a function of duty
cycle for a single-phase regulator that is adjusted for
converter efficiency.
0.60
0.55
0.50
I_P-P,N = 1
I_P-P,N = 0.50
I_P-P,N = 0.75
0.45
0.40
0.35
I_P-P,N = 0
0.30
0.25
I_P-P,N = 0.25
0.20
0.15
0.10
0.05
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DUTY CYCLE (V_IN/V_O)
FIGURE 11. NORMALIZED RMS INPUT CURRENT FOR
SINGLE PHASE CONVERTER
The normalized RMS current calculation is written as
Equation 22:
I_{IN_RMS, N} =
D
⋅
(1
–
D)
+
⎛
⎝
1^--D--2^{--⎠⎞}
⋅
I _{P P ,N} ²
(EQ. 22)
Where:
- I_MAX is the maximum continuous I_LOAD of the
converter
- I_PP,N is the ratio of inductor peak-to-peak ripple
current to I_MAX
- D is the duty cycle that is adjusted to take into
account the efficiency of the converter which is
written as:
D
=
-----^V-----^O-------
V_IN ⋅ η
(EQ. 23)
- where η is converter efficiency
Figure 12 provides the same input RMS current
information for two-phase designs.
0.3
0.2
0.1 ^IP-P,N ^{= 0.75}
I_P-P,N = 0.5
I_P-P,N = 0
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_IN/V_O)
FIGURE 12. NORMALIZED RMS INPUT CURRENT FOR
2-PHASE CONVERTER
In addition to the bulk capacitance, some low ESL
ceramic capacitance is recommended to decouple
between the drain of the high-side MOSFET and the
source of the low-side MOSFET.
MOSFET Selection and Considerations
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching
frequency, the capability of the MOSFETs to dissipate
heat, and the availability and nature of heat sinking and
air flow.
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating.
The MOSFETs used in the power stage of the converter
should have a maximum V_DS rating that exceeds the
sum of the upper voltage tolerance of the input power
source and the voltage spike that occurs when the
MOSFETs switch.
There are several power MOSFETs readily available that
are optimized for DC/DC converter applications. The
23
FN6976.1
July 28, 2010