ISL6265C_10 Datasheet, PDF (14/27 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

ISL6265C
.
VIN
PWM FREQUENCY
CONTROL
FSET
+
g_mV_IN
+
V- _{W +}
R
PWM _Q
VO
+
g_mV_O
V_R
S
+
-
C_{R TO} ^VCOMP +
PWM
CONTROL
ISL6265C
FIGURE 5. MODULATOR CIRCUITRY
RIPPLE CAPACITOR VOLTAGE C_R WINDOW VOLTAGE V_W
ERROR AMPLIFIER VOLTAGE V_COMP
PWM
FIGURE 6. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
Initialization
Once sufficient bias is applied to the VCC pin, internal
logic checks the status of critical pins to determine the
controller operation profile prior to ENABLE. These pins
include RTN1 which determines single vs two-phase
operation and OFS/VFIXEN for enabling/disabling the SVI
interface and core voltage droop. Depending on the
configuration set by these pins, the controller then
checks the state of the SVC and SVD pins to determine
the soft-start target output voltage level.
Power-On Reset
The ISL6265C requires a +5V input supply tied to VCC
and PVCC to exceed a rising power-on reset (POR)
threshold before the controller has sufficient bias to
guarantee proper operation. Once this threshold is
reached or exceeded, the ISL6265C has enough bias to
begin checking RTN1, OFS/VFIXEN, ENABLE, and SVI
inputs. Hysteresis between the rising the falling
thresholds assure the ISL6265C will not inadvertently
turn-off unless the bias voltage drops substantially (see
“Electrical Specifications” on page 12).
Core Configuration
The ISL6265C determines the core channel requirements
of the CPU based on the state of the RTN1 pin prior to
ENABLE. If RTN1 is low prior to ENABLE, both VDD0 and
VDD1 core planes are required. The core controllers
operate as independent single-phase regulators. RTN1 is
connected to the CPU Core1 negative sense point. For
single core CPU designs (uniplane), RTN1 is tied to a
+1.8V or greater supply. Prior to ENABLE, RTN1 is
detected as HIGH and the ISL6265C drives the core
controllers as a two-phase multi-phase regulator. Dual
purpose motherboard designs should include resistor
options to open the CPU Core1 negative sense and
connect the RTN1 pin to a pull-up resistor.
Mode Selection
The OFS/VFIXEN pin selects between the AMD defined
VFIX and SVI modes of operation and enables droop if
desired in SVI mode only. If OFS/VFIXEN is tied to VCC,
then SVI mode with no droop on the core output(s) is
selected. Connected to +3.3V, VFIX mode is active with
no droop on the core output(s). SVI mode with droop is
enabled when OFS/VFIXEN is tied to ground through a
resistor sized to set the core voltage positive offset.
Further information is provided in “Offset Resistor
Selection” on page 19.
Serial VID Interface
The on-board Serial VID Interface (SVI) circuitry allows
the processor to directly control the Core and
Northbridge voltage reference levels within the
ISL6265C. The SVC and SVD states are decoded
according to the PWROK and VFIXEN inputs as described
in the following sections. The ISL6265C uses a
digital-to-analog converter (DAC) to generate a
reference voltage based on the decoded SVI value. See
Figure 7 for a simple SVI interface timing diagram.
Pre-PWROK Metal VID
Assuming the OFS/VFIXEN pin is not tied to +3.3V during
controller configuration, typical motherboard start-up
begins with the controller decoding the SVC and SVD
inputs to determine the pre-PWROK metal VID setting
(see Table 1). Once the enable input (EN) exceeds the
rising enable threshold, the ISL6265C decodes and locks
the decoded value in an on-board hold register.
The internal DAC circuitry begins to ramp Core and
Northbridge planes to the decoded pre-PWROK metal
VID output level. The digital soft-start circuitry ramps the
internal reference to the target gradually at a fixed rate
of approximately 2mV/µs. The controlled ramp of all
output voltage planes reduces in-rush current during the
soft-start interval. At the end of the soft-start interval,
the PGOOD output transitions high indicating all output
planes are within regulation limits.
14
FN6976.1
July 28, 2010