ISL6265C_10 Datasheet, PDF (21/27 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

ISL6265C
with the regulator operating in single-phase mode,
transient response capability is maintained.
While operating in single-phase DE with PSI_L low, the
lower MOSFET driver switches the lower MOSFET off at
the point of zero inductor current to prevent discharge
current from flowing from the output capacitor bank
through the inductor. In DCM, switching frequency is
proportionately reduced, thus greatly reducing both
conduction and switching loss. In DCM, the switching
frequency is defined by Equation 12.
F_DCM
=
F_{----C-----C----M----}²_--
1.33²
⋅
---------²----^â‹---^L-----^â‹---^I--^O-----------
V_O
⋅
⎛
⎜
⎝
1
–
V^-V----_I^-O-_N^--_{⎠⎟⎞}
(EQ. 12)
Where F_CCM is equivalent to the Core frequency set by
Equation 3.
Fault Monitoring and Protection
The ISL6265C actively monitors Core and Northbridge
output voltages and currents to detect fault conditions.
These fault monitors trigger protective measures to
prevent damage to the processor. One common power
good indicator is provided for linking to external system
monitors.
Power-Good Signal
The power-good pin (PGOOD) is an open-drain logic
output that signals if the ISL6265C is not regulating Core
and Northbridge output voltages within the proper levels
or output current in one or more outputs has exceeded
the maximum current setpoint.
This pin must be tied to a +3.3V or +5V source through a
resistor. During shutdown and soft-start, PGOOD is
pulled low and is released high only after a successful
soft-start has raised Core and Northbridge output
voltages within operating limits. PGOOD is pulled low
when an overvoltage, undervoltage, or overcurrent (OC)
condition is detected on any output or when the
controller is disabled by a POR or forcing enable (EN)
low. Once a fault condition is triggered, the controller
acts to protect the processor. The controller latches off
and PGOOD is pulled low. Toggling EN or VCC initiates a
soft-start of all outputs. In the event of an OV, the
controller will not initiate a soft-start by toggling EN, but
requires VCC be lowered below the falling POR threshold
to reset.
Overcurrent Protection
Core and Northbridge outputs feature two different
methods of current sensing. Core output current sensing
is achieved via inductor DCR or discrete resistor sensing.
The Northbridge controller uses lower MOSFET r_DS(ON)
sensing to detect output current.
CORE OC DETECTION
Core outputs feature an OC monitor which compares a
voltage set at the OCSET pin to the voltage measured
across the current sense capacitor, V_C. When the voltage
across the current sense capacitor exceeds the
programmed trip level, the comparator signals an OC fault.
Figure 10 shows the basic OC functions within the IC.
CURRENT
SEE FIGURE 9 FOR
SENSE
ADDITIONAL DETAIL
ISP ₊
5x
ISN
V__c
5 x V_C(OC) @
OC TRIP CURRENT
BIAS
CKT
OC
-
+
6
V_OCSET
6
ISL6265C
R_BIAS 1.17V
10µA
OCSET
R_BIAS
V_OCSET
R_OCSET
FIGURE 10. OC TRIP CIRCUITRY
The sense capacitor voltage, V_C, will increase as inductor
current rises per Equation 7. When the inductor current
rises to the OC trip level, the voltage across the sense
capacitor will reach a maximum based on the resistor
ratio K. This maximum value, V_C(OC), is gained up by a
factor of 5 and compared to the static OC trip level set by
the OCSET pin.
The recommended voltage range for V_C,OC is 6mV to
25mV, which sets the resistor divider ratio K, where I_OC is
the user-defined OC trip level (see Equation 13). Typical
inductor DCR values are on the order of 1mΩ which
result in more than enough voltage drop to support this
V_C,OC range.
K = -_I-_O--^V---_C--^C---_â‹-⁽--^O_D----^C-_C----⁾-_R--
(EQ. 13)
The resistor divider components also impact time-
constant matching, these components need to meet the
parallel combination requirements of Equation 9.
Based on the selected V_C(OC) level, the required OC
monitor trip level is set. The recommended V_C(OC) level
range will result in an OC monitor trip level range of
30mV to 125mV based on the internal gain of 5.
This OC monitor trip level sets the voltage level required
at the OCSET pin to create an OC fault at the user-
defined OC trip level. A resistor divider from the RBIAS
pin to ground with the mid-point connected to OCSET
sets the voltage at the pin (see Figure 10). This voltage is
internally divided by 6 and compared with V_C(OC).
Working backwards, the voltage required at the OCSET
pin to achieve this OC trip level ranges from 180mV to
0.750mV as defined in Equation 14.
V_OCSET = V_C(OC) ⋅ 30
(EQ. 14)
The resistor divider ratio used to determine the R_BIAS and
R_OCSET values is shown in Equation 15.
21
FN6976.1
July 28, 2010