ISL6265C_10 Datasheet, PDF (16/27 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

ISL6265C
In the same manner described in “Pre-PWROK Metal
VID” on page 14, the POR circuitry impacts the internal
driver operation and PGOOD status.
SVI MODE
Once the controller has successfully soft-started and
PGOOD transitions high, the processor can assert
PWROK to signal the ISL6265C to prepare for SVI
commands. The controller actively monitors the SVI
interface for set VID commands to move the plane
voltages to start-up VID values. Details of the SVI Bus
protocol are provided in the AMD Design Guide for
Voltage Regulator Controllers Accepting Serial VID Codes
specification.
Once a set VID command is received, the ISL6265C
decodes the information to determine which output plane
is affected and the VID target required (see Table 3).The
internal DAC circuitry steps the required output plane
voltage to the new VID level. During this time, one or
more of the planes could be targeted. In the event either
core voltage plane, VDD0 or VDD1, is commanded to
power-off by serial VID commands, the PGOOD signal
remains asserted. The Northbridge voltage plane must
remain active during this time.
If the PWROK input is de-asserted, then the controller
steps both Core and Northbridge planes back to the
stored pre-PWROK metal VID level in the holding register
from initial soft-start. No attempt is made to read the
SVC and SVD inputs during this time. If PWROK is
reasserted, then the on-board SVI interface waits for a
set VID command.
If EN goes low during normal operation, all internal
drivers are tri-stated and PGOOD is pulled low. This
event clears the pre-PWROK metal VID code and forces
the controller to check SVC and SVD upon restart.
VID-On-the-Fly Transition
Once PWROK is high, the ISL6265C detects this flag and
begins monitoring the SVC and SVD pins for SVI
instructions. The microprocessor will follow the protocol
outlined in the following sections to send instructions for
VID-on-the-Fly transitions. The ISL6265C decodes the
instruction and acknowledges the new VID code. For VID
codes higher than the current VID level, the ISL6265C
begins stepping the required regulator output(s) to the
new VID target with a typical slew rate of 7.5mV/µs,
which meets the AMD requirements.
When the VID codes are lower than the current VID
level, the ISL6265C begins stepping the regulator output
to the new VID target with a typical slew rate of
-7.5mV/µs. Both Core and NB regulators are always in
CCM during a down VID transition. The AMD
requirements under these conditions do not require the
regulator to meet the minimum slew rate specification of
-5mV/µs. In either case, the slew rate is not allowed to
exceed 10mV/µs. The ISL6265C does not change the
state of PGOOD (VDDPWRGD in AMD specifications)
when a VID-on-the-fly transition occurs.
SVI WIRE Protocol
The SVI wire protocol is based on the I²C bus concept.
Two wires (serial clock (SVC) and serial data (SVD)),
carry information between the AMD processor (master)
and VR controller (slave) on the bus. The master initiates
and terminates SVI transactions and drives the clock,
SVC, during a transaction. The AMD processor is always
the master and the voltage regulators are the slaves. The
slave receives the SVI transactions and acts accordingly.
Mobile SVI wire protocol timing is based on high-speed
mode I²C. See AMD Griffin (Family 11h) processor
publications for additional details.
A POR event on VCC during normal operation will
shutdown all regulators and PGOOD is pulled low. The
pre-PWROK metal VID code is not retained.
TABLE 3. SERIAL VID CODES
SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V)
000_0000b
1.5500
010_0000b
1.1500
100_0000b
0.7500
110_0000b
0.3500*
000_0001b
1.5375
010_0001b
1.1375
100_0001b
0.7375
110_0001b
0.3375*
000_0010b
1.5250
010_0010b
1.1250
100_0010b
0.7250
110_0010b
0.3250*
000_0011b
1.5125
010_0011b
1.1125
100_0011b
0.7125
110_0011b
0.3125*
000_0100b
1.5000
010_0100b
1.1000
100_0100b
0.7000
110_0100b
0.3000*
000_0101b
1.4875
010_0101b
1.0875
100_0101b
0.6875
110_0101b
0.2875*
000_0110b
1.4750
010_0110b
1.0750
100_0110b
0.6750
110_0110b
0.2750*
000_0111b
1.4625
010_0111b
1.0625
100_0111b
0.6625
110_0111b
0.2625*
000_1000b
1.4500
010_1000b
1.0500
100_1000b
0.6500
110_1000b
0.2500*
000_1001b
1.4375
010_1001b
1.0375
100_1001b
0.6375
110_1001b
0.2375*
000_1010b
1.4250
010_1010b
1.0250
100_1010b
0.6250
110_1010b
0.2250*
000_1011b
1.4125
010_1011b
1.0125
100_1011b
0.6125
110_1011b
0.2125*
16
FN6976.1
July 28, 2010