80960CA-25 Datasheet, PDF (9/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

SPECIAL ENVIRONMENT 80960CA-25 -16
Name
A31 2
D31 0
BE3 0
WR
ADS
Type
O
S
H(Z)
R(Z)
IO
S(L)
H(Z)
R(Z)
O
S
H(Z)
R(1)
O
S
H(Z)
R(0)
O
S
H(Z)
R(1)
Table 3 80960CA Pin Description External Bus Signals
Description
ADDRESS BUS carries the physical address’ upper 30 bits A31 is the most
significant address bit A2 is the least significant During a bus access A31 2
identify all external addresses to word (4-byte) boundaries The byte enable signals
indicate the selected byte in each word During burst accesses A3 2 increment to
indicate successive data cycles
DATA BUS carries 32- 16- or 8-bit data quantities depending on bus width
configuration The least significant bit of the data is carried on D0 and the most
significant on D31 When the bus is configured for 8-bit data the lower 8 data lines
D7 0 are used For 16-bit data bus widths D15 0 are used For 32 bit bus widths the
full data bus is used
BYTE ENABLES select which of the four bytes addressed by A31 2 are active
during an access to a memory region configured for a 32-bit data-bus width BE3
applies to D31 24 BE2 applies to D23 16 BE1 applies to D15 8 BE0 applies to
D7 0
32-bit bus BE3
Byte Enable 3
enable D31 24
BE2
Byte Enable 2
enable D23 16
BE1
Byte Enable 1
enable D15 8
BE0
Byte Enable 0
enable D7 0
For accesses to a memory region configured for a 16-bit data-bus width the
processor uses the BE3 BE1 and BE0 pins as BHE A1 and BLE respectively
16-bit bus BE3
Byte High Enable (BHE)
enable D15 8
BE2
Not used (driven high or low)
BE1
Address Bit 1 (A1)
BE0
Byte Low Enable (BLE)
enable D7 0
For accesses to a memory region configured for an 8-bit data-bus width the
processor uses the BE1 and BE0 pins as A1 and A0 respectively
8-bit bus
BE3
Not used (driven high or low)
BE2
Not used (driven high or low)
BE1
Address Bit 1 (A1)
BE0
Address Bit 0 (A0)
WRITE READ is asserted for read requests and deasserted for write requests The
W R signal changes in the same clock cycle as ADS It remains valid for the entire
access in non-pipelined regions In pipelined regions W R is not guaranteed to be
valid in the last cycle of a read access
ADDRESS STROBE indicates a valid address and the start of a new bus access
ADS is asserted for the first clock of a bus access
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