80960CA-25 Datasheet, PDF (13/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

SPECIAL ENVIRONMENT 80960CA-25 -16
Table 4 80960CA Pin Description Processor Control Signals (Continued)
Name Type
Description
CLKIN
I
A(E)
H(Z)
R(Z)
CLOCK INPUT is an input for the external clock needed to run the processor The
external clock is internally divided as prescribed by the CLKMODE pin to produce
PCLK2 1
CLKMODE
I
A(L)
H(Z)
R(Z)
CLOCK MODE selects the division factor applied to the external clock input (CLKIN)
When CLKMODE is high CLKIN is divided by one to create PCLK2 1 and the
processor’s internal clock When CLKMODE is low CLKIN is divided by two to create
PCLK2 1 and the processor’s internal clock CLKMODE should be tied high or low in a
system as the clock mode is not latched by the processor If left unconnected the
processor will internally pull the CLKMODE pin low enabling the 2-x clock mode
PCLK2 1
O
S
H(Q)
R(Q)
PROCESSOR OUTPUT CLOCKS provide a timing reference for all processor inputs
and outputs All input and output timings are specified in relation to PCLK2 and
PCLK1 PCLK2 and PCLK1 are identical signals Two output pins are provided to allow
flexibility in the system’s allocation of capacitive loading on the clock PCLK2 1 may
also be connected at the processor to form a single clock signal
V_SS
V_CC
V_CCPLL
GROUND connections must be connected externally to a V_SS board plane
POWER connections must be connected externally to a V_CC board pane
V_CCPLL is a separate V_CC supply pin for the phase lock loop used in 1-x clock mode
Connecting a simple lowpass filter to V_CCPLL may help reduce clock jitter (T_CP) in
noisy environments Otherwise V_CCPLL should be connected to V_CC This pin is
implemented starting with the D-stepping See Table 13 for die stepping information
NC
NO CONNECT pins must not be connected in a system
13