80960CA-25 Datasheet, PDF (15/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

SPECIAL ENVIRONMENT 80960CA-25 -16
3 3 80960CA Mechanical Data
3 3 1 80960CA PGA Pinout
Tables 6 and 7 list the 80960CA pin names with
package location Figure 2 depicts the complete
80960CA PGA pinout as viewed from the top side of
the component (i e pins facing down) Figure 3
shows the complete 80960CA PGA pinout as
viewed from the pin-side of the package (i e pins
facing up) See Section 4 0 ELECTRICAL SPECI-
FICATIONS for specifications and recommended
connections
Table 6 80960CA PGA Pinout In Signal Order
Address Bus
Data Bus
Bus Control
Processor Control
IO
Signal Pin Signal Pin
Signal
Pin
Signal
Pin
Signal
Pin
A31
S15 D31
R3 BE3
S5
RESET
A16 DREQ3
A7
A30
Q13 D30
Q5 BE2
S6
DREQ2
B6
A29
R14 D29
S2 BE1
S7
FAIL
A2
DREQ1
A6
A28
Q14 D28
Q4 BE0
R9
DREQ0
B5
A27
S16 D27
R2
STEST
B2
A26
R15 D26
Q3 W R
S10
DACK3
A10
A25
S17 D25
S1
ONCE
C3
DACK2
A9
A24
Q15 D24
R1 ADS
R6
DACK1
A8
A23
R16 D23
Q2
CLKIN
C13 DACK0
B8
A22
R17 D22
P3 READY S3
CLKMODE C14
A21
Q16 D21
Q1 BTERM R4
PLCK1
B14 EOP TC3 A14
A20
P15 D20
P2
PLCK2
B13 EOP TC2 A13
A19
P16 D19
P1 WAIT
S12
EOP TC1 A12
A18
Q17 D18
A17
P17 D17
N2 BLAST S8
N1
V_SS
Location
EOP TC0 A11
A16
N16 D16
M1 DT R
S11 _{C7 C8 C9 C10}
XINT7
C17
A15
N17 D15
L1 DEN
S9
C11 C12 F15 G3
XINT6
C16
A14
M17 D14
L2
G15 H3 H15 J3
J15 K3 K15 L3
XINT5
B17
A13
L16 D13
K1 LOCK
S14 L15 M3 M15 Q7
XINT4
C15
A12
L17 D12
J1
Q8 Q9 Q10 Q11
XINT3
B16
A11
K17 D11
A10
J17 D10
H1
H2 HOLD
R5
V_CC
Location
XINT2
A17
XINT1
A15
A9
H17 D9
G1 HOLDA S4
B7 B9 B11 B12
XINT0
B15
A8
G17 D8
F1 BREQ
R13 C6 E15 F3 F16
A7
G16 D7
E1
G2 H16 J2 J16
K2 K16 M2 M16
NMI
D15
A6
F17 D6
F2 D C
S13 N3 N15 Q6 R7
A5
E17 D5
D1 DMA
R12 ^{R8 R10 R11}
A4
E16 D4
A3
D17 D3
E2 SUP
C1
Q12 V_CCPLL
B10
No Connect
A2
D16 D2
D2 BOFF
B1
Location
D1
C2
D0
E3
A1 A3 A4 A5 B3
B4 C4 C5 D3
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